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SPRUI07–March 2020
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List of Tables
12-24. Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode................................. 702
12-25. Register Bit Used to Choose One or Two Phases for the Receive Frame ....................................... 702
12-26. Register Bits Used to Set the Receive Word Length(s) ............................................................. 703
12-27. Register Bits Used to Set the Receive Frame Length ............................................................... 703
12-28. How to Calculate the Length of the Receive Frame ................................................................. 704
12-29. Register Bit Used to Enable/Disable the Receive Frame-Synchronization Ignore Function.................... 704
12-30. Register Bits Used to Set the Receive Companding Mode ......................................................... 705
12-31. Register Bits Used to Set the Receive Data Delay................................................................... 706
12-32. Register Bits Used to Set the Receive Sign-Extension and Justification Mode .................................. 708
12-33. Example: Use of RJUST Field With 12-Bit Data Value ABCh ...................................................... 708
12-34. Example: Use of RJUST Field With 20-Bit Data Value ABCDEh .................................................. 708
12-35. Register Bits Used to Set the Receive Interrupt Mode .............................................................. 709
12-36. Register Bits Used to Set the Receive Frame Synchronization Mode ............................................ 709
12-37. Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect on the FSR Pin ...... 710
12-38. Register Bit Used to Set Receive Frame-Synchronization Polarity ................................................ 711
12-39. Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse Width........................... 712
12-40. Register Bits Used to Set the Receive Clock Mode ................................................................. 713
12-41. Receive Clock Signal Source Selection ............................................................................... 714
12-42. Register Bit Used to Set Receive Clock Polarity ..................................................................... 714
12-43. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value ...................... 716
12-44. Register Bit Used to Set the SRG Clock Synchronization Mode................................................... 716
12-45. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock) ....................................... 717
12-46. Register Bits Used to Set the SRG Input Clock Polarity............................................................. 718
12-47. Register Bits Used to Place Transmitter in Reset Field Descriptions.............................................. 719
12-48. Register Bit Used to Enable/Disable the Digital Loopback Mode .................................................. 720
12-49. Receive Signals Connected to Transmit Signals in Digital Loopback Mode...................................... 720
12-50. Register Bits Used to Enable/Disable the Clock Stop Mode........................................................ 720
12-51. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme................................................... 721
12-52. Register Bits Used to Enable/Disable Transmit Multichannel Selection........................................... 722
12-53. Use of the Transmit Channel Enable Registers ..................................................................... 722
12-54. Register Bit Used to Choose 1 or 2 Phases for the Transmit Frame.............................................. 725
12-55. Register Bits Used to Set the Transmit Word Length(s)............................................................. 725
12-56. Register Bits Used to Set the Transmit Frame Length .............................................................. 726
12-57. How to Calculate Frame Length ........................................................................................ 726
12-58. Register Bit Used to Enable/Disable the Transmit Frame-Synchronization Ignore Function ................... 727
12-59. Register Bits Used to Set the Transmit Companding Mode ........................................................ 728
12-60. Register Bits Used to Set the Transmit Data Delay.................................................................. 729
12-61. Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode........................................ 731
12-62. Register Bits Used to Set the Transmit Interrupt Mode.............................................................. 731
12-63. Register Bits Used to Set the Transmit Frame-Synchronization Mode............................................ 732
12-64. How FSXM and FSGM Select the Source of Transmit Frame-Synchronization Pulses ........................ 732
12-65. Register Bit Used to Set Transmit Frame-Synchronization Polarity ............................................... 733
12-66. Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width ............................... 734
12-67. Register Bit Used to Set the Transmit Clock Mode .................................................................. 735
12-68. How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the MCLKX pin .......... 735
12-69. Register Bit Used to Set Transmit Clock Polarity..................................................................... 735
12-70. McBSP Emulation Modes Selectable with FREE and SOFT Bits of SPCR2 ..................................... 737
12-71. Reset State of Each McBSP Pin........................................................................................ 737
12-72. Receive Interrupt Sources and Signals ................................................................................ 742
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