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Operational Description of HRPWM
341
SPRUI07–March 2020
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High-Resolution Pulse Width Modulator (HRPWM)
The example code shown consists of two main parts:
• Initialization code (executed once)
• Run time code (typically executed within an ISR)
Example 4-6 shows the Initialization code. The first part is configured for conventional PWM. The second
part sets up the HRPWM resources.
This example assumes MEP step size of 150 ps and does not use the SFO library.
Example 4-6. HRPWM Buck Converter Initialization Code
void HrBuckDrvCnf(void)
{
// Config for conventional PWM first
EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
EPwm1Regs.TBPRD = 100; // Period set for 1000 kHz PWM
hrbuck_period = 200; // Used for Q15 to Q0 scaling
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Note: ChB is initialized here only for comparison purposes, it is not required
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // optional
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // optional
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // optional
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // optional
// Now configure the HRPWM resources
EALLOW; // Note these registers are protected
// and act only on ChA
EPwm1Regs.HRCNFG.all = 0x0; // clear all bits first
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP; // Control Falling Edge Position
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR controls the MEP
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // Shadow load on CTR=Zero
EDIS;
MEP_ScaleFactor = 66*256; // Start with typical Scale Factor
// value for 100 MHz
// Note: Use SFO functions to update
// MEP_ScaleFactor dynamically
}
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