ADC Interface
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SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
Example 7-3. Simultaneous Sampling Dual Sequencer Mode Example
Example initialization:
AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x1; // Setup simultaneous sampling mode
AdcRegs.ADCMAXCONV.all = 0x0033; // 4 double conv's each sequencer (8 total)
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup conv from channels ADCINA0 and ADCINB0
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup conv from channels ADCINA1 and ADCINB1
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup conv from channels ADCINA2 and ADCINB2
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup conv from channels ADCINA3 and ADCINB3
AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x4; // Setup conv from channels ADCINA4 and ADCINB4
AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x5; // Setup conv from channels ADCINA5 and ADCINB5
AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0x6; // Setup conv from channels ADCINA6 and ADCINB6
AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x7; // Setup conv from channels ADCINA7 and ADCINB7
If SEQ1 and SEQ2 were both executed, the results would go to the following RESULT registers:
ADCINA0 -> ADCRESULT0
ADCINB0 -> ADCRESULT1
ADCINA1 -> ADCRESULT2
ADCINB1 -> ADCRESULT3
ADCINA2 -> ADCRESULT4
ADCINB2 -> ADCRESULT5
ADCINA3 -> ADCRESULT6
ADCINB3 -> ADCRESULT7
ADCINA4 -> ADCRESULT8
ADCINB4 -> ADCRESULT9
ADCINA5 -> ADCRESULT10
ADCINB5 -> ADCRESULT11
ADCINA6 -> ADCRESULT12
ADCINB6 -> ADCRESULT13
ADCINA7 -> ADCRESULT14
ADCINB7 -> ADCRESULT15