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ADC Interface
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SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
Example 7-4. Simultaneous Sampling Cascaded Sequencer Mode Example
AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x1; // Setup simultaneous sampling mode
AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Setup cascaded sequencer mode
AdcRegs.ADCMAXCONV.all = 0x0007; // 8 double conv's (16 total)
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup conv from channels ADCINA0 and ADCINB0
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup conv from channels ADCINA1 and ADCINB1
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup conv from channels ADCINA2 and ADCINB2
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup conv from channels ADCINA3 and ADCINB3
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Setup conv from channels ADCINA4 and ADCINB4
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Setup conv from channels ADCINA5 and ADCINB5
AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Setup conv from channels ADCINA6 and ADCINB6
AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7; // Setup conv from channels ADCINA7 and ADCINB7
If the cascaded SEQ was executed, the results would go to the following ADCRESULT registers:
ADCINA0 -> ADCRESULT0
ADCINB0 -> ADCRESULT1
ADCINA1 -> ADCRESULT2
ADCINB1 -> ADCRESULT3
ADCINA2 -> ADCRESULT4
ADCINB2 -> ADCRESULT5
ADCINA3 -> ADCRESULT6
ADCINB3 -> ADCRESULT7
ADCINA4 -> ADCRESULT8
ADCINB4 -> ADCRESULT9
ADCINA5 -> ADCRESULT10
ADCINB5 -> ADCRESULT11
ADCINA6 -> ADCRESULT12
ADCINB6 -> ADCRESULT13
ADCINA7 -> ADCRESULT14
ADCINB7 -> ADCRESULT15
7.3.3 ADC Sequencer State Machine
The following description applies to the 8-state sequencers (SEQ1 or SEQ2). In this mode, SEQ1/SEQ2
can autosequence up to eight conversions of any channel in a single sequencing session (16 when
sequencers are cascaded together). Figure 7-12 shows the flow diagram. The result of each conversion is
stored in one of the eight result registers (ADCRESULT0 - ADCRESULT7 for SEQ1 and ADCRESULT8 -
ADCRESULT15 for SEQ2). These registers are filled from the lowest address to the highest address.
The number of conversions in a sequence is controlled by MAX_CONVn (a 3-bit or 4-bit field in the
ADCMAXCONV register), which is automatically loaded into the sequencing counter status bits
(SEQ_CNTR[3:0]) in the autosequence status register (ADCASEQSR) at the start of an autosequenced
conversion session. The MAX_CONVn field can have a value ranging from zero to seven (zero to fifteen
when sequencers are cascaded together). SEQ_CNTR bits count down from their loaded value as the
sequencer starts from state CONV00 and continues sequentially (CONV01, CONV02, and so on) until
SEQ_CNTR has reached zero. The number of conversions completed during an autosequencing session
is equal to (MAX_CONVn + 1).
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