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Channel Priority
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SPRUI07–March 2020
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Direct Memory Access (DMA) Module
The round-robin state machine may be reset to the idle state via the DMACTRL[PRIORITYRESET] bit.
8.5.2 Channel 1 High Priority Mode
In this mode, if a CH1 trigger occurs, the current word transfer or the current + 1 word transfer (depends
on which phase of the current DMA transfer the new CH1 trigger occurred) on any other channel is
completed (not the complete burst), execution is halted, and CH1 is serviced for the complete burst count.
When the CH1 burst is complete, execution returns to the channel that was active when the CH1 trigger
occurred. All other channels have equal priority and each enabled channel is serviced in round-robin
fashion as follows:
Higher Priority: CH1
Lower priority: CH2 → CH3 → CH4 → CH5 → CH6 → CH2 → …
Given an example where CH1, CH4 and CH5 are enabled in Channel 1 High Priority Mode and CH4 is
currently being processed. Then CH1 and CH5 both receive an interrupt trigger from their respective
peripherals before CH4 completes. CH1 and CH5 are now both pending. When the current CH4 word
transfer is completed, regardless of whether the DMA has completed the entire CH4 burst, CH4 execution
will be suspended and CH1 will be serviced. After the CH1 burst completes, CH4 will resume execution.
Upon completion of CH4, CH5 will be serviced. After CH5 completes, if there are no more channels
pending, the round-robin state machine will enter an idle state.
Typically Channel 1 would be used in this mode for the ADC, since its data rate is so high. However,
Channel 1 High Priority Mode may be used in conjunction with any peripheral.
NOTE: High-priority mode and ONESHOT mode may not be used at the same time on channel 1.
Other channels may use ONESHOT mode when channel 1 is in high-priority mode.
8.6 Address Pointer and Transfer Control
The DMA state machine is, at its most basic level, two nested loops. The inner loop transfers a burst of
data when a peripheral interrupt trigger is received. A burst is the smallest amount of data that can be
transferred at one time and its size is defined by the BURST_SIZE register for each channel. The
BURST_SIZE register allows a maximum of 32 sixteen-bit words to be transferred in one burst. The outer
loop, whose size is set by the TRANSFER_SIZE register for each channel, defines how many bursts are
performed in the entire transfer. Since TRANSFER_SIZE is a 16-bit register, the total size of a transfer
allowed is well beyond any practical requirement. One CPU interrupt is generated, if enabled, for each
transfer. This interrupt can be configured to occur at the beginning or the end of the transfer via the
MODE.CHx[CHINTMODE] bit.
In the default setting of the MODE.CHx[ONESHOT] bit, the DMA transfers one burst of data each time a
peripheral interrupt trigger is received. After the burst is completed, the state machine moves on to the
next pending channel in the priority scheme, even if another trigger for the channel just completed is
pending. This feature keeps any single channel from monopolizing the DMA bus. If a transfer of more than
the maximum number of words per burst is desired for a single trigger, the MODE.CHx[ONESHOT] bit can
be set to complete the entire transfer when triggered. Care is advised when using this mode, since this
can create a condition where one trigger uses up the majority of the DMA bandwidth.
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