CPU Arbitration
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SPRUI07–March 2020
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Direct Memory Access (DMA) Module
8.4.2 For All Other Peripherals/Memories
• If the CPU and the DMA make an access to the same interface in the same cycle, the DMA has
priority and the CPU is stalled.
• If a CPU access to an interface is in progress and another CPU access to the same interface is
pending, for example, the CPU is performing a write operation and a read operation from the CPU is
pending, then a DMA access to that same interface has priority over the pending CPU access when
the current CPU access completes.
NOTE: If the CPU is performing a read-modify-write operation and the DMA performs a write to the
same location, the DMA write may be lost if the operation occurs in between the CPU read
and the CPU write. For this reason, it is advised not to mix such CPU accesses with DMA
accesses to the same locations.
In the case of RAM, a ping-pong scheme can be implemented to avoid the CPU and the DMA accessing
the same RAM block concurrently, thus avoiding any stalls or corruption issues.
8.5 Channel Priority
Two priority schemes exist when determining channel priority: Round-robin mode and Channel 1 high-
priority mode.
8.5.1 Round-Robin Mode
In this mode, all channels have equal priority and each enabled channel is serviced in round-robin fashion
as follows:
CH1 → CH2 → CH3 → CH4 → CH5 → CH6 → CH1 → CH2 → …
In the case above, after each channel has transferred a burst of words, the next channel is serviced. You
can specify the size of the burst for each channel. Once CH6 (or the last enabled channel) has been
serviced, and no other channels are pending, the round-robin state machine enters an idle state.
From the idle state, channel 1 (if enabled) is always serviced first. However, if the DMA is currently
processing another channel x, all other pending channels between x and the end of the round are serviced
before CH1. It is in this sense that all the channels are of equal priority. For instance, take an example
where CH1, CH4, and CH5 are enabled in round-robin mode and CH4 is currently being processed. Then
CH1 and CH5 both receive an interrupt trigger from their respective peripherals before CH4 completes.
CH1 and CH5 are now both pending. When CH4 completes its burst, CH5 will be serviced next. Only after
CH5 completes will CH1 be serviced. Upon completion of CH1, if there are no more channels pending, the
round-robin state machine will enter an idle state.
A more complicated example is shown below:
• Assume all channels are enabled, and the DMA is in an idle state,
• Initially a trigger occurs on CH1, CH3, and CH5 on the same cycle,
• When the CH1 burst transfer starts, requests from CH3 and CH5 are pending,
• Before completion of the CH1 burst, the DMA receives a request from CH2. Now the pending requests
are from CH2, CH3, and CH5,
• After completing the CH1 burst, CH2 will be serviced since it is next in the round-robin scheme after
CH1.
• After the burst from CH2 is finished, the CH3 burst will be serviced, followed by CH5 burst.
• Now while the CH5 burst is being serviced, the DMA receives a request from CH1, CH3, and CH6.
• The burst from CH6 will start after the completion of the CH5 burst since it is the next channel after
CH5 in the round-robin scheme.
• This will be followed by the CH1 burst and then the CH3 burst
• After the CH3 burst finishes, assuming no more triggers have occurred, the round-robin state machine
will enter an idle state.
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