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CPU Arbitration
501
SPRUI07–March 2020
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Direct Memory Access (DMA) Module
For example, to transfer 128 16-bit words from ADC to RAM a channel can be configured to transfer 8
bursts of 16 words/burst. This will give:
8 bursts * [(4 cycles/word * 16 words/burst) + 1] = 520 cycles
If instead the channel were configured to transfer the same amount of data 32 bits at a time (the word size
is configured to 32 bits) the transfer would take:
8 bursts * [(4 cycles/word * 8 words/burst) + 1] = 264 cycles
8.4 CPU Arbitration
Typically, DMA activity is independent of the CPU activity. Under the circumstance where both the DMA
and the CPU are attempting to access memory or a peripheral register within the same interface
concurrently, an arbitration procedure will occur. The one exception is with the memory mapped (PF0)
ADC registers, which do not create a conflict when read by both the CPU and the DMA simultaneously,
even if different addresses are accessed. Any combined accesses between the different interfaces, or
where the CPU access is outside of the interface that the DMA is accessing do not create a conflict.
The interfaces that internally contain conflicts are:
• XINTF Memory Zones 0, 6, and 7
• L4 RAM
• L5 RAM
• L6 RAM
• L7 RAM
• Peripheral Frame 3 (McBSP-A, McBSP-B)
NOTE: The ePWM/HRPWM are not present on all devices and/or revisions. See the TMS320x28xx,
28xxx device Peripheral Reference Guide ( SPRU566) for specifics.
8.4.1 For the External Memory Interface (XINTF) Zones
• If the CPU and the DMA attempt an access to any of the XINTF zones on the same cycle, the DMA is
serviced first, followed by all the pending CPU accesses (in the proper priority order for CPU accesses:
write → read → fetch).
• If CPU accesses to an XINTF zone are pending or being processed by the XINTF and a DMA access
to an XINTF zone is attempted, the DMA access is stalled until all CPU pending accesses are
completed. For example, if a CPU write and read access is pending and a fetch is in progress, first the
fetch is completed, then the CPU write is performed, then the CPU read is performed, and then the
DMA access is performed.
• There is a 1 cycle stall if simultaneous write accesses by the CPU and the DMA are attempted.
If the DMA or CPU is used to write to the XINTF zones, then the write buffer of the XINTF can help to
avoid CPU or DMA stalls. If the CPU or DMA are performing reads from XINTF, then significant stalls can
occur. The only concern here is if the DMA is stalled and the DMA misses other higher priority DMA
events such as servicing the ADC which can generate data at a high rate. In such situations, the DMA
should not be used to transfer data on XINTF, if the stalls are too long that there is potential to miss other
DMA events.
The DMA does not support abort mechanisms for DMA reads from XINTF. If the DMA is performing an
access to one of the XINTF zones and the DMA access is stalled (XREADY not responding) then the CPU
can issue a HARDRESET that would abort the access. HARDRESET behaves like a System Reset on the
DMA. Likewise, a HARDRESET needs to be applied to the XINTF hence releasing the peripheral from the
struck ready condition. Any data that is write buffered or pending on the XINTF or DMA will be lost.
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