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Data Packing Examples
739
SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
NOTE:
1. The necessary duration of the active-low period of XRST or RRST is at least two
MCLKR/CLKX cycles.
2. The appropriate bits in serial port configuration registers SPCR[1,2], PCR, RCR[1,2],
XCR[1,2], and SRGR[1,2] must only be modified when the affected portion of the serial
port is in its reset state.
3. In most cases, the data transmit registers (DXR[1,2]) must be loaded by the CPU or by
the DMA controller only when the transmitter is enabled (XRST = 1). An exception to
this rule is when these registers are used for companding internal data (see
Section 12.3.2.2).
4. The bits of the channel control registers—MCR[1,2], RCER[A-H], XCER[A-H]—can be
modified at any time as long as they are not being used by the current
reception/transmission in a multichannel selection mode.
12.10.2.4 Resetting the Transmitter While the Receiver is Running
Example 12-1 shows values in the control registers that reset and configure the transmitter while the
receiver is running.
Example 12-1. Resetting and Configuring McBSP Transmitter While McBSP Receiver Running
SPCR1 = 0001h SPCR2 = 0030h ; The receiver is running with the receive interrupt (RINT) triggered by
the ; receiver ready bit (RRDY). The transmitter is in its reset state . The transmit interrupt
(XINT) will be triggered by the transmit frame-
sync ; error bit (XSYNCERR). PCR = 0900h ; Transmit frame synchronization is generated internally
according to the ; FSGM bit of SRGR2. ; The transmit clock is driven by an external source. ; The
receive clock continues to be driven by sample rate generator. The input clock ; of the sample rate
generator is supplied by the CPU clock SRGR1 = 0001h SRGR2 = 2000h ; The CPU clock is the input clock
for the sample rate generator. The sample ; rate generator divides the CPU clock by 2 to generate its
output clock (CLKG). ; Transmit frame synchronization is tied to the automatic copying of data from ;
the DXR(s) to the XSR(s). XCR1 = 0740h XCR2 = 8321h ; The transmit frame has two phases. Phase 1 has
eight 16-bit words. Phase 2 ; has four 12-bit words. There is 1-
bit data delay between the start of a ; frame-
sync pulse and the first data bit ; transmitted. SPCR2 = 0031h ; The transmitter is taken out of
reset.
12.11 Data Packing Examples
This section shows two ways to implement data packing in the McBSP.
12.11.1 Data Packing Using Frame Length and Word Length
Frame length and word length can be manipulated to effectively pack data. For example, consider a
situation where four 8-bit words are transferred in a single-phase frame as shown in Figure 12-61. In this
case:
• (R/X)PHASE = 0: Single-phase frame
• (R/X)FRLEN1 = 0000011b: 4-word frame
• (R/X)WDLEN1 = 000b: 8-bit words
Four 8-bit data words are transferred to and from the McBSP by the CPU or by the DMA controller. Thus,
four reads from DRR1 and four writes to DXR1 are necessary for each frame.
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