Special Case: External Device is the Transmit Frame Master
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
Table 12-75. McBSP Mode Selection (continued)
Register Bits Used for Mode Selection
MCR1 bit 9,0 MCR2 bit 9,1,0
No. McBSP
Word Size
RMCME RMCM XMCME XMCM Mode and Function Description
selected in XCERs
1 1 1 11 Symmetric transmit, receive
Continuous Mode - Transmit
1 0 1 0 Multi-Channel Mode is OFF
All 128 channels are active and enabled
12.14 Special Case: External Device is the Transmit Frame Master
Care must be taken if the transmitter expects a frame sync from an external device. After the transmitter
comes out of reset (XRST = 1), it waits for a frame sync from the external device. If the first frame sync
arrives very shortly after the transmitter is enabled, the CPU or DMA controller may not have a chance to
service DXR. In this case, the transmitter shifts out the default data in XSR instead of the desired value,
which has not yet arrived in DXR. This causes problems in some applications, as the first data element in
the frame is invalid. The data stream appears element-shifted (the first data word may appear in the
second channel instead of the first).
To ensure proper operation when the external device is the frame master, you must assure that DXR is
already serviced with the first word when a frame sync occurs. To do so, you can keep the transmitter in
reset until the first frame sync is detected. Upon detection of the first frame sync, the McBSP generates an
interrupt to the CPU. Within the interrupt service routine, the transmitter is taken out of reset (XRST = 1).
This assures that the transmitter does not begin data transfers at the data pin during the first frame sync
period. This also provides almost an entire frame period for the DSP to service DXR with the first word
before the second frame sync occurs. The transmitter only begins data transfers upon receiving the
second frame sync. At this point, DXR is already serviced with the first word.
The interrupt service routine must first be setup according to the description in . Then follow this modified
procedure for proper initialization:
1. Ensure that no portion of the McBSP is using the internal sample rate generator signal CLKG and the
internal frame sync generator signal FSG (GRST = FRST = 0). The respective portion of the McBSP
needs to be in reset (XRST = 0 and/or RRST = 0).
2. Program SRGR and other control registers as required. Ensure the internal sample rate generator and
the internal frame sync generator are still in reset (GRST = FRST = 0). Also ensure the respective
portion of the McBSP is still in reset in this step (XRST = 0 and/or RRST = 0).
3. Program the XINTM bits to 2h in SPCR to generate an interrupt to the CPU upon detection of a
transmit frame sync. Do not enable the XINT interrupt in the interrupt enable register (IER) in this step.
4. Wait for proper internal synchronization. If the external device provides the bit clock, wait for two CLKR
or CLKX cycles. If the McBSP generates the bit clock as a clock master, wait for two CLKSRG cycles.
In this case, the clock source to the sample rate generator (CLKSRG) is selected by the CLKSM bit in
SRGR.
5. Skip this step if the bit clock is provided by the external device. This step only applies if the McBSP is
the bit clock master and the internal sample rate generator is used.
a. Start the sample rate generator by setting the GRST bit to 1. Wait two CLKG bit clocks for
synchronization. CLKG is the output of the sample rate generator.
b. On the next rising edge of CLKSRG, CLKG transitions to 1 and starts clocking with a frequency
equal to 1/(CLKGDV + 1) of the sample rate generator source clock CLKSRG.
6. A transmit sync error (XSYNCERR) may occur when it is enabled for the first time after device reset.
The purpose of this step is to clear any potential XSYNCERR that occurs on the transmitter at this
time:
a. Set the XRST bit to 1 to enable the transmitter.
b. Wait for any unexpected frame sync error to occur. If the external device provides the bit clock,
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