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McBSP Registers
749
SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
Table 12-77. Serial Port Control 1 Register (SPCR1) Field Descriptions (continued)
Bit Field Value Description
14-13 RJUST 0-3h Receive sign-extension and justification mode bits. During reception, RJUST determines how data
is justified and bit filled before being passed to the data receive registers (DRR1, DRR2).
RJUST is ignored if you enable a companding mode with the RCOMPAND bits. In a companding
mode, the 8-bit compressed data in RBR1 is expanded to left-justified 16-bit data in DRR1.
For more details about the effects of RJUST, see Section 12.8.13.
0 Right justify the data and zero fill the MSBs.
1h Right justify the data and sign-extend the data into the MSBs.
2h Left justify the data and zero fill the LSBs.
3h Reserved (do not use)
12-11 CLKSTP 0-3h Clock stop mode bits. CLKSTP allows you to use the clock stop mode to support the SPI master-
slave protocol. If you will not be using the SPI protocol, you can clear CLKSTP to disable the clock
stop mode.
In the clock stop mode, the clock stops at the end of each data transfer. At the beginning of each
data transfer, the clock starts immediately (CLKSTP = 10b) or after a half-cycle delay (CLKSTP =
11b).
For more details, see Section 12.8.5.
0-1h Clock stop mode is disabled.
2h Clock stop mode, without clock delay
3h Clock stop mode, with half-cycle clock delay
10-8 Reserved 0 Reserved bits (not available for your use). They are read-only bits and return 0s when read.
7 DXENA DX delay enabler mode bit. DXENA controls the delay enabler for the DX pin. The enabler creates
an extra delay for turn-on time (for the length of the delay, see the device-specific data sheet). For
more details about the effects of DXENA, see Section 12.9.14.
0 DX delay enabler off
1 DX delay enabler on
6 Reserved 0 Reserved
5-4 RINTM 0-3h Receive interrupt mode bits. RINTM determines which event in the McBSP receiver generates a
receive interrupt (RINT) request. If RINT is properly enabled inside the CPU, the CPU services the
interrupt request; otherwise, the CPU ignores the request.
0 The McBSP sends a receive interrupt (RINT) request to the CPU when the RRDY bit changes from
0 to 1, indicating that receive data is ready to be read (the content of RBR[1,2] has been copied to
DRR[1,2]):
Regardless of the value of RINTM, you can check RRDY to determine whether a word transfer is
complete.
The McBSP sends a RINT request to the CPU when 16 enabled bits have been received on the DR
pin.
1h In the multichannel selection mode, the McBSP sends a RINT request to the CPU after every 16-
channel block is received in a frame.
Outside of the multichannel selection mode, no interrupt request is sent.
2h The McBSP sends a RINT request to the CPU when each receive frame-synchronization pulse is
detected. The interrupt request is sent even if the receiver is in its reset state.
3h The McBSP sends a RINT request to the CPU when the RSYNCERR bit is set, indicating a receive
frame-synchronization error.
Regardless of the value of RINTM, you can check RSYNCERR to determine whether a receive
frame-synchronization error occurred.
3 RSYNCERR Receive frame-sync error bit. RSYNCERR is set when a receive frame-sync error is detected by the
McBSP. If RINTM = 11b, the McBSP sends a receive interrupt (RINT) request to the CPU when
RSYNCERR is set. The flag remains set until you write a 0 to it or reset the receiver.
0 No error
1 Receive frame-synchronization error. For more details about this error, see Section 12.5.3.
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