McBSP Registers
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
Table 12-77. Serial Port Control 1 Register (SPCR1) Field Descriptions (continued)
Bit Field Value Description
2 RFULL Receiver full bit. RFULL is set when the receiver is full with new data and the previously received
data has not been read (receiver-full condition). For more details about this condition, see
Section 12.5.2.
0 No receiver-full condition
1 Receiver-full condition: RSR[1,2] and RBR[1,2] are full with new data, but the previous data in
DRR[1,2] has not been read.
1 RRDY Receiver ready bit. RRDY is set when data is ready to be read from DRR[1,2]. Specifically, RRDY
is set in response to a copy from RBR1 to DRR1.
If the receive interrupt mode is RINTM = 00b, the McBSP sends a receive interrupt request to the
CPU when RRDY changes from 0 to 1.
Also, when RRDY changes from 0 to 1, the McBSP sends a receive synchronization event (REVT)
signal to the DMA controller.
0 Receiver not ready
When the content of DRR1 is read, RRDY is automatically cleared.
1 Receiver ready: New data can be read from DRR[1,2].
Important: If both DRRs are required (word length larger than 16 bits), the CPU or the DMA
controller must read from DRR2 first and then from DRR1. As soon as DRR1 is read, the next
RBR-to-DRR copy is initiated. If DRR2 is not read first, the data in DRR2 is lost.
0 RRST Receiver reset bit. You can use RRST to take the McBSP receiver into and out of its reset state.
This bit has a negative polarity; RRST = 0 indicates the reset state.
To read about the effects of a receiver reset, see Section 12.10.2.
0 If you read a 0, the receiver is in its reset state.
If you write a 0, you reset the receiver.
1 If you read a 1, the receiver is enabled.
If you write a 1, you enable the receiver by taking it out of its reset state.
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