McBSP Registers
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
12.15.12 XCERs Used in a Transmit Multichannel Selection Mode
For multichannel selection operation, the assignment of channels to the XCERs depends on whether 32 or
128 channels are individually selectable, as defined by the XMCME bit. These two cases are shown in
Table 12-96. The table shows which block of channels is assigned to each XCER that is used. For each
XCER, the table shows which channel is assigned to each of the bits.
NOTE: When XMCM = 11b (for symmetric transmission and reception), the transmitter uses the
receive channel enable registers (RCERs) to enable channels and uses the XCERs to
unmask channels for transmission.
Table 12-96. Use of the Transmit Channel Enable Registers
Number of
Selectable
Channels
Block Assignments Channel Assignments
XCERx Block Assigned Bit in XCERx Channel Assigned
32
(XMCME = 0)
XCERA Channels n to (n + 15) XCE0 Channel n
XCE1 Channel (n + 1)
XCE2 Channel (n + 2)
: :
When XMCM = 01b or 10b, the block
of channels is chosen with the
XPABLK bits. When XMCM = 11b,
the block is chosen with the RPABLK
bits.
XCE15 Channel (n + 15)
XCERB Channels m to (m + 15) XCE0 Channel m
XCE1 Channel (m + 1)
XCE2 Channel (m + 2)
: :
When XMCM = 01b or 10b, the block
of channels is chosen with the
XPBBLK bits. When XMCM = 11b,
the block is chosen with the RPBBLK
bits.
XCE15 Channel (m + 15)
128
(XMCME = 1)
XCERA Block 0 XCE0 Channel 0
XCE1 Channel 1
XCE2 Channel 2
: :
XCE15 Channel 15
XCERB Block 1 XCE0 Channel 16
XCE1 Channel 17
XCE2 Channel 18
: :
XCE15 Channel 31
XCERC Block 2 XCE0 Channel 32
XCE1 Channel 33
XCE2 Channel 34
: :
XCE15 Channel 47
XCERD Block 3 XCE0 Channel 48
XCE1 Channel 49
XCE2 Channel 50
: :
XCE15 Channel 63
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