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20
SPRUI07–March 2020
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List of Figures
9-13. SPIRXBUF Register...................................................................................................... 572
9-14. SPITXBUF Register ...................................................................................................... 573
9-15. SPIDAT Register.......................................................................................................... 574
9-16. SPIFFTX Register ........................................................................................................ 575
9-17. SPIFFRX Register ........................................................................................................ 577
9-18. SPIFFCT Register ........................................................................................................ 579
9-19. SPIPRI Register........................................................................................................... 580
10-1. SCI CPU Interface........................................................................................................ 582
10-2. Serial Communications Interface (SCI) Module Block Diagram .................................................... 583
10-3. Typical SCI Data Frame Formats....................................................................................... 585
10-4. Idle-Line Multiprocessor Communication Format..................................................................... 587
10-5. Double-Buffered WUT and TXSHF..................................................................................... 588
10-6. Address-Bit Multiprocessor Communication Format ................................................................. 589
10-7. SCI Asynchronous Communications Format.......................................................................... 590
10-8. SCI RX Signals in Communication Modes ............................................................................ 590
10-9. SCI TX Signals in Communications Mode ............................................................................ 591
10-10. SCI FIFO Interrupt Flags and Enable Logic........................................................................... 593
10-11. SCICCR Register ......................................................................................................... 597
10-12. SCICTL1 Register ........................................................................................................ 599
10-13. SCIHBAUD Register ..................................................................................................... 601
10-14. SCILBAUD Register...................................................................................................... 602
10-15. SCICTL2 Register ........................................................................................................ 603
10-16. SCIRXST Register........................................................................................................ 605
10-17. SCIRXEMU Register ..................................................................................................... 607
10-18. SCIRXBUF Register...................................................................................................... 608
10-19. SCITXBUF Register ...................................................................................................... 609
10-20. SCIFFTX Register ........................................................................................................ 610
10-21. SCIFFRX Register........................................................................................................ 612
10-22. SCIFFCT Register ........................................................................................................ 614
10-23. SCIPRI Register .......................................................................................................... 615
11-1. Multiple I2C Modules Connected ....................................................................................... 617
11-2. I2C Module Conceptual Block Diagram................................................................................ 619
11-3. Clocking Diagram for the I2C Module.................................................................................. 619
11-4. The Roles of the Clock Divide-Down Values (ICCL and ICCH) .................................................... 620
11-5. Bit Transfer on the I2C bus.............................................................................................. 621
11-6. I2C Module START and STOP Conditions............................................................................ 623
11-7. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown)............................. 624
11-8. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR).............................................. 624
11-9. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR) ............................................ 624
11-10. I2C Module Free Data Format (FDF = 1 in I2CMDR)................................................................ 625
11-11. Repeated START Condition (in This Case, 7-Bit Addressing Format) ............................................ 625
11-12. Synchronization of Two I2C Clock Generators During Arbitration ................................................. 626
11-13. Arbitration Procedure Between Two Master-Transmitters........................................................... 627
11-14. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit....................................... 628
11-15. Enable Paths of the I2C Interrupt Requests .......................................................................... 629
11-16. Backwards Compatibility Mode Bit, Slave Transmitter............................................................... 630
11-17. I2C_FIFO_interrupt ....................................................................................................... 631
11-18. I2COAR Register ......................................................................................................... 634
11-19. I2CIER Register........................................................................................................... 635
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