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SPRUI07–March 2020
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List of Figures
7-28. ADCOFFTRIM Register.................................................................................................. 494
8-1. DMA Block Diagram...................................................................................................... 497
8-2. Peripheral Interrupt Trigger Input Diagram............................................................................ 498
8-3. 4-Stage Pipeline DMA Transfer......................................................................................... 500
8-4. 4-Stage Pipeline With One Read Stall (McBSP as source)......................................................... 500
8-5. DMA State Diagram ...................................................................................................... 507
8-6. ADC Sync Input Diagram................................................................................................ 509
8-7. Overrun Detection Logic ................................................................................................. 510
8-8. DMACTRL Register ...................................................................................................... 515
8-9. DEBUGCTRL Register................................................................................................... 516
8-10. REVISION Register....................................................................................................... 517
8-11. PRIORITYCTRL1 Register .............................................................................................. 518
8-12. PRIORITYSTAT Register................................................................................................ 519
8-13. MODE Register ........................................................................................................... 520
8-14. CONTROL Register ...................................................................................................... 523
8-15. BURST_SIZE Register................................................................................................... 526
8-16. BURST_COUNT Register ............................................................................................... 527
8-17. SRC_BURST_STEP Register........................................................................................... 528
8-18. DST_BURST_STEP Register........................................................................................... 529
8-19. TRANSFER_SIZE Register ............................................................................................. 530
8-20. TRANSFER_COUNT Register.......................................................................................... 531
8-21. SRC_TRANSFER_STEP Register ..................................................................................... 532
8-22. DST_TRANSFER_STEP Register ..................................................................................... 533
8-23. SRC_WRAP_SIZE Register............................................................................................. 534
8-24. SRC_WRAP_COUNT Register ......................................................................................... 535
8-25. SRC_WRAP_STEP Register............................................................................................ 536
8-26. DST_WRAP_SIZE Register............................................................................................. 537
8-27. DST_WRAP_COUNT Register ......................................................................................... 538
8-28. DST_WRAP_STEP Register............................................................................................ 539
8-29. SRC_BEG_ADDR_SHADOW Register................................................................................ 540
8-30. SRC_ADDR_SHADOW Register....................................................................................... 541
8-31. SRC_BEG_ADDR Register ............................................................................................. 542
8-32. SRC_ADDR Register..................................................................................................... 543
8-33. DST_BEG_ADDR_SHADOW Register ................................................................................ 544
8-34. DST_ADDR_SHADOW Register ....................................................................................... 545
8-35. DST_BEG_ADDR Register.............................................................................................. 546
8-36. DST_ADDR Register..................................................................................................... 547
9-1. SPI CPU Interface ........................................................................................................ 550
9-2. SPI Interrupt Flags and Enable Logic Generation.................................................................... 552
9-3. SPI Master/Slave Connection........................................................................................... 553
9-4. Serial Peripheral Interface Block Diagram............................................................................. 554
9-5. SPICLK Signal Options .................................................................................................. 558
9-6. SPI: SPICLK-LSPCLK Characteristic When (BRR + 1) is Odd, BRR > 3, and CLKPOLARITY = 1........... 559
9-7. Five Bits per Character................................................................................................... 561
9-8. SPICCR Register ......................................................................................................... 564
9-9. SPICTL Register.......................................................................................................... 566
9-10. SPISTS Register.......................................................................................................... 568
9-11. SPIBRR Register ......................................................................................................... 570
9-12. SPIRXEMU Register ..................................................................................................... 571
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