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Texas Instruments TMS320 2833 Series User Manual

Texas Instruments TMS320 2833 Series
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21
SPRUI07March 2020
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Copyright © 2020, Texas Instruments Incorporated
List of Figures
11-20. I2CSTR Register.......................................................................................................... 636
11-21. I2CCLKL Register ........................................................................................................ 640
11-22. I2CCLKH Register ........................................................................................................ 641
11-23. I2CCNT Register.......................................................................................................... 642
11-24. I2CDRR Register ......................................................................................................... 643
11-25. I2CSAR Register.......................................................................................................... 644
11-26. I2CDXR Register.......................................................................................................... 645
11-27. I2CMDR Register ......................................................................................................... 646
11-28. I2CISRC Register......................................................................................................... 650
11-29. I2CEMDR Register ....................................................................................................... 651
11-30. I2CPSC Register.......................................................................................................... 652
11-31. I2CFFTX Register ........................................................................................................ 653
11-32. I2CFFRX Register ........................................................................................................ 655
12-1. Conceptual Block Diagram of the McBSP............................................................................. 660
12-2. McBSP Data Transfer Paths ............................................................................................ 661
12-3. Companding Processes.................................................................................................. 662
12-4. μ-Law Transmit Data Companding Format............................................................................ 662
12-5. A-Law Transmit Data Companding Format ........................................................................... 662
12-6. Two Methods by Which the McBSP Can Compand Internal Data ................................................. 663
12-7. Example - Clock Signal Control of Bit Transfer Timing.............................................................. 663
12-8. McBSP Operating at Maximum Packet Frequency .................................................................. 665
12-9. Single-Phase Frame for a McBSP Data Transfer .................................................................... 666
12-10. Dual-Phase Frame for a McBSP Data Transfer ...................................................................... 667
12-11. Implementing the AC97 Standard With a Dual-Phase Frame ...................................................... 667
12-12. Timing of an AC97-Standard Data Transfer Near Frame Synchronization ....................................... 668
12-13. McBSP Reception Physical Data Path................................................................................. 668
12-14. McBSP Reception Signal Activity....................................................................................... 668
12-15. McBSP Transmission Physical Data Path............................................................................. 669
12-16. McBSP Transmission Signal Activity................................................................................... 669
12-17. Conceptual Block Diagram of the Sample Rate Generator ......................................................... 671
12-18. Possible Inputs to the Sample Rate Generator and the Polarity Bits.............................................. 673
12-19. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 ............................ 675
12-20. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 ............................ 676
12-21. Overrun in the McBSP Receiver........................................................................................ 678
12-22. Overrun Prevented in the McBSP Receiver........................................................................... 679
12-23. Possible Responses to Receive Frame-Synchronization Pulses................................................... 679
12-24. An Unexpected Frame-Synchronization Pulse During a McBSP Reception...................................... 680
12-25. Proper Positioning of Frame-Synchronization Pulses................................................................ 681
12-26. Data in the McBSP Transmitter Overwritten and Thus Not Transmitted .......................................... 681
12-27. Underflow During McBSP Transmission............................................................................... 682
12-28. Underflow Prevented in the McBSP Transmitter ..................................................................... 683
12-29. Possible Responses to Transmit Frame-Synchronization Pulses.................................................. 683
12-30. An Unexpected Frame-Synchronization Pulse During a McBSP Transmission.................................. 684
12-31. Proper Positioning of Frame-Synchronization Pulses................................................................ 685
12-32. Alternating Between the Channels of Partition A and the Channels of Partition B .............................. 687
12-33. Reassigning Channel Blocks Throughout a McBSP Data Transfer................................................ 688
12-34. McBSP Data Transfer in the 8-Partition Mode........................................................................ 689
12-35. Activity on McBSP Pins for the Possible Values of XMCM ......................................................... 692
12-36. Typical SPI Interface ..................................................................................................... 693

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Texas Instruments TMS320 2833 Series Specifications

General IconGeneral
BrandTexas Instruments
ModelTMS320 2833 Series
CategoryController
LanguageEnglish

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