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SPRUI07–March 2020
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List of Figures
12-37. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 0, and CLKRP = 0............................. 695
12-38. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 0, CLKRP = 1 ...................................... 695
12-39. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 1, and CLKRP = 0............................. 695
12-40. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 1, CLKRP = 1 ...................................... 695
12-41. SPI Interface with McBSP Used as Master ........................................................................... 697
12-42. SPI Interface With McBSP Used as Slave ............................................................................ 698
12-43. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 0 ..................................................... 705
12-44. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 1 ..................................................... 705
12-45. Companding Processes for Reception and for Transmission....................................................... 706
12-46. Range of Programmable Data Delay................................................................................... 707
12-47. 2-Bit Data Delay Used to Skip a Framing Bit ......................................................................... 707
12-48. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge.... 712
12-49. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods ........................................ 713
12-50. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge.... 715
12-51. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 0 .................................................... 727
12-52. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 1 .................................................... 728
12-53. Companding Processes for Reception and for Transmission....................................................... 728
12-54. μ-Law Transmit Data Companding Format............................................................................ 729
12-55. A-Law Transmit Data Companding Format ........................................................................... 729
12-56. Range of Programmable Data Delay................................................................................... 730
12-57. 2-Bit Data Delay Used to Skip a Framing Bit ......................................................................... 730
12-58. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge.... 734
12-59. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods ........................................ 734
12-60. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge.... 736
12-61. Four 8-Bit Data Words Transferred To/From the McBSP ........................................................... 740
12-62. One 32-Bit Data Word Transferred To/From the McBSP ........................................................... 740
12-63. 8-Bit Data Words Transferred at Maximum Packet Frequency..................................................... 741
12-64. Configuring the Data Stream of as a Continuous 32-Bit Word ..................................................... 741
12-65. Receive Interrupt Generation............................................................................................ 742
12-66. Transmit Interrupt Generation........................................................................................... 742
12-67. Data Receive Registers (DRR2 and DRR1) .......................................................................... 747
12-68. Data Transmit Registers (DXR2 and DXR1).......................................................................... 747
12-69. Serial Port Control 1 Register (SPCR1) ............................................................................... 748
12-70. Serial Port Control 2 Register (SPCR2) ............................................................................... 751
12-71. Receive Control Register 1 (RCR1).................................................................................... 753
12-72. Receive Control Register 2 (RCR2).................................................................................... 754
12-73. Transmit Control 1 Register (XCR1) ................................................................................... 756
12-74. Transmit Control 2 Register (XCR2) .................................................................................. 757
12-75. Sample Rate Generator 1 Register (SRGR1)......................................................................... 759
12-76. Sample Rate Generator 2 Register (SRGR2)......................................................................... 759
12-77. Multichannel Control 1 Register (MCR1) ............................................................................. 761
12-78. Multichannel Control 2 Register (MCR2) .............................................................................. 763
12-79. Pin Control Register (PCR) ............................................................................................. 765
12-80. Receive Channel Enable Registers (RCERA...RCERH) ............................................................ 767
12-81. Transmit Channel Enable Registers (XCERA...XCERH)............................................................ 769
12-82. McBSP Interrupt Enable Register (MFFINT).......................................................................... 771
13-1. eCAN Block Diagram and Interface Circuit............................................................................ 775
13-2. CAN Data Frame ......................................................................................................... 776
13-3. Architecture of the eCAN Module....................................................................................... 777
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