XINTF Registers
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SPRUI07–March 2020
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External Interface (XINTF)
Table 14-11. XTIMING7 Register Field Descriptions (continued)
Bit Field Type Reset Description
14 USEREADY R/W 1h
Determines if accesses to the zone will sample or ignore the
XREADY input signal.
0h = The XREADY signal is ignored when accesses are made to the
zone.
1h = The XREADY signal can further extend the active portion of an
access to the zone past the minimum defined by the XRDACTIVE
and XWRACTIVE fields.
13-12 XRDLEAD R/W 1h Two-bit field that defines the read cycle lead wait state period, in
XTIMCLK cycles. If the X2TIMING bit is set, then the number of wait
states are doubled.
See Section 14.4 for minimum requirements in different modes.
See Table 14-12.
11-9 XRDACTIVE R/W 1h Three-bit field that defines the read cycle active wait state period, in
XTIMCLK cycles. The active period is by default 1 XTIMCLK cycle.
Therefore, the total active period is (1 + XWRACTIVE) XTIMCLK
cycles. If the X2TIMING bit is set, then the number of wait states are
doubled.
See Section 14.4 for minimum requirements in different modes.
See Table 14-13.
8-7 XRDTRAIL R/W 1h Two-bit field that defines the read cycle trail wait state period, in
XTIMCLK cycles. If the X2TIMING bit is set, then the number of wait
states are doubled.
See Section 14.4 for minimum requirements in different modes.
See Table 14-14.
6-5 XWRLEAD R/W 1h Two-bit field that defines the write cycle lead wait state period, in
XTIMCLK cycles.
If the X2TIMING bit is set, then the number of wait states are
doubled.
See Section 14.4 for minimum requirements in different modes.
See Table 14-15.
4-2 XWRACTIVE R/W 1h Three-bit field that defines the write cycle active wait state period, in
XTIMCLK cycles. The active period is by default 1 XTIMCLK cycle.
Therefore, the total active period is (1 + XWRACTIVE) XTIMCLK
cycles. If the X2TIMING bit is set, then the number of wait states are
doubled.
See Section 14.4 for minimum requirements in different modes.
See Table 14-16.
1-0 XWRTRAIL R/W 1h Two-bit field that defines the write cycle trail wait state period, in
XTIMCLK cycles. If the X2TIMING bit is set, then the number of wait
states are doubled.
See Section 14.4 for minimum requirements in different modes.
See Table 14-17.
Table 14-12. XRDLEAD
X2TIMING Read Lead Period
00 X Invalid
01 0 1 XTIMCLK cycle
1 2 XTIMCLK cycles
10 0 2 XTIMCLK cycles
1 4 XTIMCLK cycles
11 0 3 XTIMCLK cycles
1 6 XTIMCLK cycles (default)
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