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General-Purpose Input/Output (GPIO)
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SPRUI07–March 2020
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System Control and Interrupts
1.4.5 GPIO and Peripheral Multiplexing (MUX)
Up to three different peripheral functions are multiplexed along with a general input/output (GPIO) function
per pin. This allows you to pick and choose a peripheral mix that will work best for the particular
application.
Table 1-47, Table 1-48, and Table 1-49 show an overview of the possible multiplexing combinations
sorted by GPIO pin. The second column indicates the I/O name of the pin on the device. Since the I/O
name is unique, it is the best way to identify a particular pin. Therefore, the register descriptions in this
section only refer to the GPIO name of a particular pin. The MUX register and particular bits that control
the selection for each pin are indicated in the first column.
For example, the multiplexing for the GPIO7 pin is controlled by writing to GPAMUX[15:14]. By writing to
these bits, the pin is configured as either GPIO7, or one of up to three peripheral functions. The GPIO7
pin can be configured as follows:
GPAMUX1[15:14] Bit Setting Pin Functionality Selected
If GPAMUX1[15:14] = 0,0 Pin configured as GPIO7
If GPAMUX1[15:14] = 0,1 Pin configured as EPWM4B (O)
If GPAMUX1[15:14] = 1,0 Pin configured as MCLKRA (I/O)
If GPAMUX1[15:14] = 1,1 Pin configured as ECAP2 (I/O)
All devices in the 2833x, 2823x family have the same multiplexing scheme. The only difference is that if a
peripheral is not available on a particular device, that MUX selection is reserved on that device and should
not be used.
NOTE: If you should select a reserved GPIO MUX configuration that is not mapped to a peripheral,
the state of the pin will be undefined and the pin may be driven. Reserved configurations are
for future expansion and should not be selected. In the device MUX tables (Table 1-47,
Table 1-48, and Table 1-49) these options are indicated as "Reserved".
Some peripherals can be assigned to more than one pin via the MUX registers. For example, the CAP1
function can be assigned to either the GPIO5 or GPIO24 pin, depending on individual system
requirements as shown below:
Pin Assigned to CAP1 MUX Configuration
Choice 1 GPIO5 GPAMUX1[11:10] = 1,1
or Choice 2 GPIO24 GPAMUX2[17:16] = 0,1
If no pin is configured as an input to a peripheral, or if more than one pin is configured as an input for the
same peripheral, then the input to the peripheral will either default to a 0 or a 1 as shown in Table 1-46.
For example, if ECAP1 were assigned to both GPIO5 and GPIO24, the input to the eCAP1 peripheral
would default to a high state as shown in Table 1-46 and the input would not be connected to GPIO5 or
GPIO24.
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