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33
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
List of Figures
List of Figures
1-1. Block Diagram............................................................................................................. 110
1-2. Example: SPIDELAY – 0xFFF7F448 .................................................................................. 111
2-1. Architectural Block Diagram............................................................................................. 114
2-2. PCR MasterID Filtering .................................................................................................. 119
2-3. Memory-Map .............................................................................................................. 121
2-4. EPC Integration Diagram ................................................................................................ 132
2-5. Hardware Memory Initialization Protocol .............................................................................. 137
2-6. EXTCTL_Out_Port Register [offset = 404h]........................................................................... 148
2-7. LPO and Clock Detection, Untrimmed HF LPO ...................................................................... 149
2-8. SYS Pin Control Register 1 (SYSPC1) (offset = 00h) ............................................................... 153
2-9. SYS Pin Control Register 2 (SYSPC2) (offset = 04h) ............................................................... 153
2-10. SYS Pin Control Register 3 (SYSPC3) (offset = 08h) ............................................................... 154
2-11. SYS Pin Control Register 4 (SYSPC4) (offset = 0Ch)............................................................... 154
2-12. SYS Pin Control Register 5 (SYSPC5) (offset = 10h) ............................................................... 155
2-13. SYS Pin Control Register 6 (SYSPC6) (offset = 14h) ............................................................... 155
2-14. SYS Pin Control Register 7 (SYSPC7) (offset = 18h) ............................................................... 156
2-15. SYS Pin Control Register 8 (SYSPC8) (offset = 1Ch)............................................................... 156
2-16. SYS Pin Control Register 9 (SYSPC9) (offset = 20h) ............................................................... 157
2-17. Clock Source Disable Register (CSDIS) (offset = 30h).............................................................. 158
2-18. Clock Source Disable Set Register (CSDISSET) (offset = 34h).................................................... 159
2-19. Clock Source Disable Clear Register (CSDISCLR) (offset = 38h) ................................................. 160
2-20. Clock Domain Disable Register (CDDIS) (offset = 3Ch) ............................................................ 161
2-21. Clock Domain Disable Set Register (CDDISSET) (offset = 40h)................................................... 163
2-22. Clock Domain Disable Clear Register (CDDISCLR) (offset = 44h) ................................................ 165
2-23. GCLK1, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) (offset = 48h) ................................. 167
2-24. Peripheral Asynchronous Clock Source Register (VCLKASRC) (offset = 4Ch).................................. 168
2-25. RTI Clock Source Register (RCLKSRC) (offset = 50h).............................................................. 169
2-26. Clock Source Valid Status Register (CSVSTAT) (offset = 54h) .................................................... 170
2-27. Memory Self-Test Global Control Register (MSTGCR) (offset = 58h)............................................. 171
2-28. Memory Hardware Initialization Global Control Register (MINITGCR) (offset = 5Ch)........................... 172
2-29. MBIST Controller/Memory Initialization Enable Register (MSINENA) (offset = 60h) ............................ 173
2-30. MSTC Global Status Register (MSTCGSTAT) (offset = 68h)....................................................... 174
2-31. Memory Hardware Initialization Status Register (MINISTAT) (offset = 6Ch) ..................................... 175
2-32. PLL Control Register 1 (PLLCTL1) (offset = 70h).................................................................... 175
2-33. PLL Control Register 2 (PLLCTL2) (offset = 74h).................................................................... 177
2-34. SYS Pin Control Register 10 (SYSPC10) (offset = 78h) ............................................................ 178
2-35. Die Identification Register, Lower Word (DIEIDL) [offset = 7Ch]................................................... 179
2-36. Die Identification Register, Upper Word (DIEIDH) [offset = 80h]................................................... 179
2-37. LPO/Clock Monitor Control Register (LPOMONCTL) (offset = 088h) ............................................. 180
2-38. Clock Test Register (CLKTEST) (offset = 8Ch)....................................................................... 183
2-39. DFT Control Register (DFTCTRLREG) (offset = 90h) .............................................................. 185
2-40. DFT Control Register 2 (DFTCTRLREG2) (offset = 94h) .......................................................... 186
2-41. General Purpose Register (GPREG1) (offset = A0h) ............................................................... 187
2-42. System Software Interrupt Request 1 Register (SSIR1) (offset = B0h) ........................................... 188
2-43. System Software Interrupt Request 2 Register (SSIR2) (offset = B4h) ........................................... 189
2-44. System Software Interrupt Request 3 Register (SSIR3) (offset = B8h) ........................................... 190
2-45. System Software Interrupt Request 4 Register (SSIR4) (offset = BCh)........................................... 191
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