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SPRUI07–March 2020
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Copyright © 2020, Texas Instruments Incorporated
Contents
Contents
Preface....................................................................................................................................... 36
1 System Control and Interrupts ............................................................................................. 38
1.1 Flash and OTP Memory Blocks .......................................................................................... 39
1.1.1 Flash Memory...................................................................................................... 39
1.1.2 OTP Memory....................................................................................................... 39
1.1.3 Flash and OTP Power Modes ................................................................................... 39
1.1.4 Flash and OTP Registers ........................................................................................ 44
1.2 Code Security Module (CSM)............................................................................................. 49
1.2.1 Functional Description ............................................................................................ 49
1.2.2 CSM Impact on Other On-Chip Resources.................................................................... 52
1.2.3 Incorporating Code Security in User Applications ............................................................ 53
1.2.4 Do's and Don'ts to Protect Security Logic...................................................................... 58
1.2.5 CSM Features - Summary ....................................................................................... 58
1.3 Clocking and System Control............................................................................................. 59
1.3.1 Clocking ............................................................................................................ 59
1.3.2 OSC and PLL Block............................................................................................... 66
1.3.3 Low-Power Modes Block......................................................................................... 74
1.3.4 Watchdog Block ................................................................................................... 76
1.3.5 32-Bit CPU Timers 0/1/2 ......................................................................................... 81
1.4 General-Purpose Input/Output (GPIO) .................................................................................. 86
1.4.1 GPIO Module Overview .......................................................................................... 86
1.4.2 Configuration Overview........................................................................................... 92
1.4.3 Digital General Purpose I/O Control ............................................................................ 93
1.4.4 Input Qualification ................................................................................................. 95
1.4.5 GPIO and Peripheral Multiplexing (MUX)...................................................................... 99
1.4.6 Register Bit Definitions.......................................................................................... 104
1.5 Peripheral Frames ........................................................................................................ 129
1.5.1 Peripheral Frame Registers .................................................................................... 129
1.5.2 EALLOW-Protected Registers ................................................................................. 131
1.5.3 Device Emulation Registers .................................................................................... 135
1.5.4 Write-Followed-by-Read Protection ........................................................................... 137
1.6 Peripheral Interrupt Expansion (PIE)................................................................................... 138
1.6.1 Overview of the PIE Controller................................................................................. 138
1.6.2 Vector Table Mapping........................................................................................... 141
1.6.3 Interrupt Sources................................................................................................. 143
1.6.4 PIE Configuration and Control Registers ..................................................................... 153
1.6.5 External Interrupt Control Registers .......................................................................... 163
2 Boot ROM ........................................................................................................................ 166
2.1 Boot ROM Memory Map ................................................................................................. 167
2.1.1 On-Chip Boot ROM IQmath Tables ........................................................................... 167
2.1.2 CPU Vector Table ............................................................................................... 170
2.2 Bootloader Features...................................................................................................... 171
2.2.1 Bootloader Functional Operation .............................................................................. 171
2.2.2 Bootloader Device Configuration .............................................................................. 173
2.2.3 PLL Multiplier and DIVSEL Selection ......................................................................... 173
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