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SPRUI07–March 2020
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Copyright © 2020, Texas Instruments Incorporated
Contents
9.5.1 SPI Base Addresses ............................................................................................ 562
9.5.2 SPI_REGS Registers............................................................................................ 563
10 Serial Communications Interface (SCI) ................................................................................ 581
10.1 Introduction ................................................................................................................ 582
10.2 Architecture................................................................................................................ 584
10.3 SCI Module Signal Summary ........................................................................................... 584
10.4 Configuring Device Pins ................................................................................................. 584
10.5 Multiprocessor and Asynchronous Communication Modes ......................................................... 584
10.6 SCI Programmable Data Format ....................................................................................... 585
10.7 SCI Multiprocessor Communication.................................................................................... 585
10.7.1 Recognizing the Address Byte................................................................................ 586
10.7.2 Controlling the SCI TX and RX Features.................................................................... 586
10.7.3 Receipt Sequence .............................................................................................. 586
10.8 Idle-Line Multiprocessor Mode .......................................................................................... 586
10.8.1 Idle-Line Mode Steps........................................................................................... 587
10.8.2 Block Start Signal............................................................................................... 588
10.8.3 Wake-UP Temporary (WUT) Flag ............................................................................ 588
10.8.4 Receiver Operation............................................................................................. 588
10.9 Address-Bit Multiprocessor Mode ...................................................................................... 588
10.9.1 Sending an Address............................................................................................ 588
10.10 SCI Communication Format............................................................................................. 589
10.10.1 Receiver Signals in Communication Modes ............................................................... 590
10.10.2 Transmitter Signals in Communication Modes ............................................................ 590
10.11 SCI Port Interrupts ....................................................................................................... 591
10.12 SCI Baud Rate Calculations ............................................................................................ 592
10.13 SCI Enhanced Features ................................................................................................. 592
10.13.1 SCI FIFO Description......................................................................................... 592
10.13.2 SCI Auto-Baud................................................................................................. 594
10.13.3 Autobaud-Detect Sequence ................................................................................. 594
10.14 SCI Registers ............................................................................................................. 595
10.14.1 SCI Base Addresses.......................................................................................... 595
10.14.2 SCI_REGS Registers......................................................................................... 596
11 Inter-Integrated Circuit Module (I2C) ................................................................................... 616
11.1 Introduction ................................................................................................................ 617
11.1.1 Features.......................................................................................................... 617
11.1.2 Features Not Supported ....................................................................................... 618
11.1.3 Functional Overview............................................................................................ 618
11.1.4 Clock Generation ............................................................................................... 619
11.1.5 I2C Clock Divider Registers (I2CCLKL and I2CCLKH) .................................................... 620
11.2 Configuring Device Pins ................................................................................................. 620
11.3 I2C Module Operational Details......................................................................................... 621
11.3.1 Input and Output Voltage Levels ............................................................................. 621
11.3.2 Data Validity ..................................................................................................... 621
11.3.3 Operating Modes ............................................................................................... 621
11.3.4 I2C Module START and STOP Conditions.................................................................. 622
11.3.5 Serial Data Formats ............................................................................................ 623
11.3.6 NACK Bit Generation........................................................................................... 625
11.3.7 Clock Synchronization ......................................................................................... 626
11.3.8 Arbitration........................................................................................................ 626
11.3.9 Digital Loopback Mode......................................................................................... 627
11.4 Interrupt Requests Generated by the I2C Module.................................................................... 628
11.4.1 Basic I2C Interrupt Requests.................................................................................. 628
11.4.2 I2C FIFO Interrupts............................................................................................. 630
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