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SPRUI07–March 2020
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Contents
8.7 ADC Sync Feature........................................................................................................ 508
8.8 Overrun Detection Feature .............................................................................................. 510
8.9 Register Descriptions..................................................................................................... 510
8.9.1 DMACTRL Register (Offset = 1000h) [reset = 0h] .......................................................... 515
8.9.2 DEBUGCTRL Register (Offset = 1001h) [reset = 0h]....................................................... 516
8.9.3 REVISION Register (Offset = 1002h) [reset = 0h]........................................................... 517
8.9.4 PRIORITYCTRL1 Register (Offset = 1004h) [reset = 0h] .................................................. 518
8.9.5 PRIORITYSTAT Register (Offset = 1006h) [reset = 0h].................................................... 519
8.9.6 MODE Register (Offset = 1020h + [i * E3h]) [reset = 0h]................................................... 520
8.9.7 CONTROL Register (Offset = 1021h + [i * E3h]) [reset = 0h] ............................................. 523
8.9.8 BURST_SIZE Register (Offset = 1022h + [i * E3h]) [reset = 0h] .......................................... 526
8.9.9 BURST_COUNT Register (Offset = 1023h + [i * E3h]) [reset = 0h] ...................................... 527
8.9.10 SRC_BURST_STEP Register (Offset = 1024h + [i * E3h]) [reset = 0h]................................. 528
8.9.11 DST_BURST_STEP Register (Offset = 1025h + [i * E3h]) [reset = 0h] ................................. 529
8.9.12 TRANSFER_SIZE Register (Offset = 1026h + [i * E3h]) [reset = 0h].................................... 530
8.9.13 TRANSFER_COUNT Register (Offset = 1027h + [i * E3h]) [reset = 0h] ................................ 531
8.9.14 SRC_TRANSFER_STEP Register (Offset = 1028h + [i * E3h]) [reset = 0h] ........................... 532
8.9.15 DST_TRANSFER_STEP Register (Offset = 1029h + [i * E3h]) [reset = 0h]............................ 533
8.9.16 SRC_WRAP_SIZE Register (Offset = 102Ah + [i * E3h]) [reset = 0h] .................................. 534
8.9.17 SRC_WRAP_COUNT Register (Offset = 102Bh + [i * E3h]) [reset = 0h]............................... 535
8.9.18 SRC_WRAP_STEP Register (Offset = 102Ch + [i * E3h]) [reset = 0h] ................................. 536
8.9.19 DST_WRAP_SIZE Register (Offset = 102Dh + [i * E3h]) [reset = 0h]................................... 537
8.9.20 DST_WRAP_COUNT Register (Offset = 102Eh + [i * E3h]) [reset = 0h] ............................... 538
8.9.21 DST_WRAP_STEP Register (Offset = 102Fh + [i * E3h]) [reset = 0h].................................. 539
8.9.22 SRC_BEG_ADDR_SHADOW Register (Offset = 1030h + [i * E3h]) [reset = 0h]...................... 540
8.9.23 SRC_ADDR_SHADOW Register (Offset = 1032h + [i * E3h]) [reset = 0h] ............................. 541
8.9.24 SRC_BEG_ADDR Register (Offset = 1034h + [i * E3h]) [reset = 0h].................................... 542
8.9.25 SRC_ADDR Register (Offset = 1036h + [i * E3h]) [reset = 0h]........................................... 543
8.9.26 DST_BEG_ADDR_SHADOW Register (Offset = 1038h + [i * E3h]) [reset = 0h] ...................... 544
8.9.27 DST_ADDR_SHADOW Register (Offset = 103Ah + [i * E3h]) [reset = 0h] ............................. 545
8.9.28 DST_BEG_ADDR Register (Offset = 103Ch + [i * E3h]) [reset = 0h] ................................... 546
8.9.29 DST_ADDR Register (Offset = 103Eh + [i * E3h]) [reset = 0h]........................................... 547
9 Serial Peripheral Interface (SPI).......................................................................................... 548
9.1 Introduction ................................................................................................................ 549
9.1.1 Features........................................................................................................... 549
9.1.2 Block Diagram.................................................................................................... 550
9.2 System-Level Integration ................................................................................................ 550
9.2.1 SPI Module Signals.............................................................................................. 550
9.2.2 Configuring Device Pins ........................................................................................ 551
9.2.3 SPI Interrupts..................................................................................................... 551
9.3 SPI Operation ............................................................................................................. 553
9.3.1 Introduction to Operation ....................................................................................... 553
9.3.2 Master Mode ..................................................................................................... 555
9.3.3 Slave Mode....................................................................................................... 555
9.3.4 Data Format ...................................................................................................... 556
9.3.5 Baud Rate Selection ............................................................................................ 557
9.3.6 SPI Clocking Schemes.......................................................................................... 558
9.3.7 SPI FIFO Description............................................................................................ 559
9.4 Programming Procedure................................................................................................. 560
9.4.1 Initialization Upon Reset ........................................................................................ 560
9.4.2 Configuring the SPI.............................................................................................. 560
9.4.3 Data Transfer Example ......................................................................................... 561
9.5 SPI Registers.............................................................................................................. 562
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