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SPRUI07–March 2020
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Contents
6.5.1 Position Counter Operating Modes............................................................................ 398
6.5.2 Position Counter Latch.......................................................................................... 400
6.5.3 Position Counter Initialization .................................................................................. 402
6.5.4 eQEP Position-compare Unit................................................................................... 403
6.6 eQEP Edge Capture Unit................................................................................................ 404
6.7 eQEP Watchdog .......................................................................................................... 408
6.8 Unit Timer Base........................................................................................................... 409
6.9 eQEP Interrupt Structure ................................................................................................ 410
6.10 eQEP Registers........................................................................................................... 410
6.10.1 eQEP Base Addresses ........................................................................................ 410
6.10.2 EQEP_REGS Registers ....................................................................................... 411
7 Analog-to-Digital Converter (ADC) ...................................................................................... 445
7.1 Features and Implementation ........................................................................................... 446
7.2 ADC Circuit ................................................................................................................ 448
7.2.1 ADC Clocking and Sample Rate Calculations ............................................................... 448
7.2.2 ADC Sample and Hold Circuit and Modeling ................................................................ 450
7.2.3 Reference Selection............................................................................................. 455
7.2.4 Power-up Sequence and Power Modes ...................................................................... 456
7.2.5 Calibration and Offset Correction.............................................................................. 457
7.3 ADC Interface ............................................................................................................. 461
7.3.1 Input Trigger Description ....................................................................................... 461
7.3.2 Autoconversion Sequencer Principle of Operation.......................................................... 462
7.3.3 ADC Sequencer State Machine................................................................................ 469
7.3.4 Interrupt Operation During Sequenced Conversions ....................................................... 474
7.3.5 ADC to DMA Interface .......................................................................................... 475
7.4 ADC Registers ............................................................................................................ 477
7.4.1 ADCTRL1 Register (Offset = 0h) [reset = 0h]................................................................ 478
7.4.2 ADCTRL2 Register (Offset = 1h) [reset = 0h]................................................................ 480
7.4.3 ADCMAXCONV Register (Offset = 2h) [reset = 0h]......................................................... 483
7.4.4 ADCCHSELSEQ1 Register (Offset = 3h) [reset = 0h] ...................................................... 485
7.4.5 ADCCHSELSEQ2 Register (Offset = 4h) [reset = 0h] ...................................................... 486
7.4.6 ADCCHSELSEQ3 Register (Offset = 5h) [reset = 0h] ...................................................... 487
7.4.7 ADCCHSELSEQ4 Register (Offset = 6h) [reset = 0h] ...................................................... 488
7.4.8 ADCASEQSR Register (Offset = 7h) [reset = 0h] ........................................................... 489
7.4.9 ADCRESULT_0 to ADCRESULT_15 Register (Offset = 8h to 17h) [reset = 0h]........................ 490
7.4.10 ADCTRL3 Register (Offset = 18h) [reset = 0h] ............................................................. 491
7.4.11 ADCST Register (Offset = 19h) [reset = 0h] ................................................................ 492
7.4.12 ADCREFSEL Register (Offset = 1Ch) [reset = 0h]......................................................... 493
7.4.13 ADCOFFTRIM Register (Offset = 1Dh) [reset = 0h] ....................................................... 494
8 Direct Memory Access (DMA) Module ................................................................................ 495
8.1 Introduction ................................................................................................................ 496
8.2 Architecture................................................................................................................ 497
8.2.1 Block Diagram.................................................................................................... 497
8.2.2 Peripheral Interrupt Event Trigger Sources .................................................................. 498
8.2.3 DMA Bus.......................................................................................................... 499
8.3 Pipeline Timing and Throughput........................................................................................ 500
8.4 CPU Arbitration ........................................................................................................... 501
8.4.1 For the External Memory Interface (XINTF) Zones ......................................................... 501
8.4.2 For All Other Peripherals/Memories........................................................................... 502
8.5 Channel Priority ........................................................................................................... 502
8.5.1 Round-Robin Mode.............................................................................................. 502
8.5.2 Channel 1 High Priority Mode.................................................................................. 503
8.6 Address Pointer and Transfer Control ................................................................................. 503
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