Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 75
3.6.5.8.4 Condition Flags
These instructions do not change the flags.
Examples
REV R3, R7 ; Reverse byte order of value in R7 and write it to R3
REV16 R0, R0 ; Reverse byte order of each 16-bit halfword in R0
REVSH R0, R5 ; Reverse Signed Halfword
REVHS R3, R7 ; Reverse with Higher or Same condition
RBIT R7, R8 ; Reverse bit order of value in R8 and write the result to R7.
3.6.5.9 TST and TEQ
Test bits and Test Equivalence.
3.6.5.9.1 Syntax
TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
where:
cond is an optional condition code, see Conditional Execution, page 55.
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See Flexible Second Operand, page 51 for details of the options.
3.6.5.9.2 Operation
These instructions test the value in a register against
Operand2
. They update the condition flags based on
the result, but do not write the result to a register.
The
TST
instruction performs a bitwise AND operation on the value in
Rn
and the value of
Operand2
. This
is the same as the
ANDS
instruction, except that it discards the result.
To test whether a bit of
Rn
is 0 or 1, use the
TST
instruction with an
Operand2
constant that has that bit set
to 1 and all other bits cleared to 0.
The
TEQ
instruction performs a bitwise Exclusive OR operation on the value in
Rn
and the value of
Operand2
. This is the same as the
EORS
instruction, except that it discards the result.
Use the
TEQ
instruction to test if two values are equal without affecting the V or C flags.
TEQ
is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive
OR of the sign bits of the two operands.
3.6.5.9.3 Restrictions
Do not use SP and do not use PC
.
3.6.5.9.4 Condition Flags
These instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of
Operand2
, see Flexible Second Operand, page 51
• do not affect the V flag.
Examples
TST R0, #0x3F8 ; Perform bitwise AND of R0 value to 0x3F8,
; APSR is updated but result is discarded
TEQEQ R10, R9 ; Conditionally test if value in R10 is equal to
; value in R9, APSR is updated but result is discarded.
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