Microsemi SmartFusion2 - Figure 24 ICER Register Bit Assignments; Figure 25 ISPR Register Bit Assignments

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 96
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not
enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never
activates the interrupt, regardless of its priority.
3.7.1.4 Interrupt Clear-enable Registers
The NVIC_ICER0-NVIC_ICER7 registers disable interrupts, and show which interrupts are enabled. See
the register summary in Ta bl e 40 , page 95 for the register attributes.
The bit assignments are:
Figure 24 • ICER Register Bit Assignments
3.7.1.5 Interrupt Set-pending Registers
The NVIC_ISPR0-NVIC_ISPR7 registers force interrupts into the pending state, and show which
interrupts are pending. See the register summary in Table 40, page 95 for the register attributes.
The bit assignments are:
Figure 25 • ISPR Register Bit Assignments
Table 42 • NVIC_ISER Bit Assignments
Bits Name Function
[31:0] SETENA Interrupt set-enable bits.
Write:
0: no effect
1: enable interrupt.
Read:
0: interrupt disabled
1: interrupt enabled.
Table 43 • NVIC_ICER Bit Assignments
Bits Name Function
[31:0] CLRENA Interrupt clear-enable bits.
Write:
0: no effect
1: disable interrupt.
Read:
0: interrupt disabled
1: interrupt enabled.
CLRENA bits
31 0
SETPEND bits
31 0