Communication Block
UG0331 User Guide Revision 15.0 600
17.5.5 Word Data Register
This register writes a word (32 bits) to the Transmit FIFO or reads a word from the Receive FIFO. If the
Transmit FIFO has less than 4 spaces available at the time of a write, an OVERFLOW will be set in the
STATUS register. Similarly, if Receive FIFO has less than 4 bytes available at the time of a read, an
UNDERFLOW will be generated.
The LSB is transferred on the DATA bus first. When the DATA32 register is written, the command bit
(Bit 8 on DATA) is set to 0, indicating that it is data. Writes to this register automatically set the SIZETX to
1 (4 bytes) and reads set the SIZERX to 1 (4 bytes).
17.5.6 Frame/Command Byte Register
This register writes a byte to the Transmit FIFO or reads a byte from the Receive FIFO. If the Transmit
FIFO is full at the time of a write, an OVERFLOW will be set in the STATUS register. Similarly, if Receive
FIFO is empty at the time of a read, an UNDERFLOW will be generated.
When the FRAME_START8 register is written, the command bit (Bit 8 on DATA) is set to 1, indicating the
start of a frame, that is, the command byte. Writes to this register automatically set the SIZETX to 0 (1
byte), and reads set the SIZERX to 0 (1 byte). The STATUS register bit 7 indicates that this byte is a
command.
17.5.7 Frame/Command Word Register
This register writes a word (32-bits) to the Transmit FIFO or reads a word from the Receive FIFO. If the
Transmit FIFO has less than four spaces available at the time of a write, an OVERFLOW will be set in
STATUS register. Similarly, if Receive FIFO has less than four bytes available at the time of a read, an
UNDERFLOW will be generated.
The least significant bit (LSB) is transferred on the DATA bus first. When the FRAME_START32 register
is written, the command bit is set to 1, indicating the start of a frame, that is, command byte. The
command bit (Bit 8 on DATA) will be set on the first byte for writes.
Writes to this register automatically sets the SIZETX to 1 (4 bytes) and reads set the SIZERX to 1
(4 bytes). The STATUS register bit 7 indicates that this word is a command.
Table 598 • DATA32
Bit
Number Name R/W Reset Value Description
[31:0] DATA32 R/W 0x00000000 Write: Writes a word to the MSS COMM_BLK Transmit FIFO
Read: Read a word from the MSS COMM_BLK Receive FIFO
Table 599 • FRAME_START8
Bit
Number Name R/W Reset Value Description
[7:0] FRAME_START8 R/W 0x00 Write: Writes byte to the MSS COMM_BLK transmit FIFO
Read: Read a byte from the MSS COMM_BLK receive FIFO
Table 600 • FRAME_START32
Bit
Number Name R/W Reset Value Description
[31:0] FRAME_START32 R/W 0x00000000 Write: Writes a word to the MSS COMM_BLK transmit FIFO
Read: Reads a word from the MSS COMM_BLK receive FIFO
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