Microsemi SmartFusion2 - Figure 30 ACTLR Bit Assignments; Figure 31 CPUID Register Bit Assignments; Table 51 ACTLR Bit Assignments

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 102
See the register summary in the preceding table for the ACTLR attributes. The bit assignments are:
Figure 30 • ACTLR Bit Assignments
3.7.2.2 CPUID Base Register
The CPUID register contains the processor part number, version, and implementation information. See
the register summary in Ta bl e 50 , page 102 for its attributes. The bit assignments are:
Figure 31 • CPUID Register Bit Assignments
Table 51 • ACTLR Bit Assignments
Bits Name Function
[31:3] Reserved
[2] DISFOLD When set to 1, disables the ability of the Cortex-M3 processor to execute an IT
instruction in parallel with a neighboring instruction.
[1] DISDEFWBUF When set to 1, disables write buffer use during default memory map accesses. This
causes all BusFaults to be precise BusFaults but decreases performance because
any store to memory must complete before the processor can execute the next
instruction. This bit only affects write buffers implemented in the Cortex-M3
processor.
[0] DISMCYCINT When set to 1, disables interruption of load multiple and store multiple instructions.
This increases the interrupt latency of the processor because any LDM or STM must
complete before the processor can stack the current state and enter the interrupt
handler.
Table 52 • CPUID register Bit Assignments
Bits Name Function
[31:24] Implementer Implementer code:
0x41 = ARM
[23:20] Variant Variant number, the r value in the rnpn product
revision identifier:
0x2 = Revision 2
[19:16] Constant Reads as
0xF
[15:4] PartNo Part number of the processor:
0xC23 = Cortex-M3
DISFOLD
DISDEFWBUF
DISMCYCINT
31 3210
Reserved
31 16 15 4 3 0
Implementer
RevisionPartNo
24 23 20 19
Variant Constant