Microsemi SmartFusion2 - Features; Figure 121 HPDMA Controller Block Diagram; Functional Description

High Performance DMA Controller
UG0331 User Guide Revision 15.0 237
8.1 Features
• Faster read/write operations with two concurrent AHB masters
• 32-bit AHB operation at 200 MHz
• 32-bit APB slave interface for control and status registers at 25/50/100/200 MHz
• Internal 32-bit control, status, and debug registers
• Single DMA channel with four queuing HPDMA descriptors, serviced with round robin priority
• Up to 64 KB data transfer in single channel request
• 32-byte internal data buffer
• Supports word aligned data transfers
• Interrupts for DMA transfer complete and transfer errors
• DMA transfer pause
• Individual descriptor reset
• Data transfer in little-endian format
8.2 Functional Description
HPDMA has a single channel which can process up to four service requests (HPDMA descriptor) in a
round robin fashion. To process each request, HPDMA descriptor is configured by an AHB bus matrix
master through APB interface. The AHB bus matrix master can be Cortex-M3, USB, Ethernet and Fabric
master. The HPDMA APB interface is connected on APB_1, which is an AHB to APB bridge as shown in
the preceding figure. HPDMA then reads data from the source memory and transfers data to the
destination.
This section provides the detailed description of the HPDMA.
Architecture Overview
HPDMA mainly consists of following sub-blocks, as shown in the following figure:
• Interfaces
• Configuration and Status Registers
• DMA Controller
• Write Buffer Controller
• Read Buffer Controller
• Data Buffer
Figure 121 • HPDMA Controller Block Diagram
APB Interface
APB Slave
Configuration and
Status Registers
DMA
Controller
Write Buffer
Controller
Read Buffer
Controller
Data Buffer
MUX
Logic
AHB
Master 1
AHB
Master 2
AHB Bus Matrix
MSS DDR
Bridge
HPDMA