Microsemi SmartFusion2 - Figure 231 Pmbus and Smbus Devices Interface

Inter-Integrated Circuit Peripherals
UG0331 User Guide Revision 15.0 543
For an SMBus application, it is advised to choose a PCLK so that the SCL transfers data at near the
maximum frequency to ensure that other potential clock-stretching devices on the bus do not slow the
clock frequency to below the minimum allowed SMBus clock frequency.
Figure 231 • PMBus and SMBus Devices Interface
15.2.4.4 I
2
C Interrupts
There are three interrupt signals for each I
2
C peripheral (I2C_0_INT, I2C_0_SMBALERT, and
I2C_0_SMBSUS). These signals are generated by MSS I2C_0 and are mapped to INTISR 4, INTISR 5,
and INTISR 6 in the Cortex-M3 processor NVIC controller. The I2C_1_INT, I2C_1_SMBALERT, and
I2C_1_SMBSUS signals are generated by MSS I2C_1 and are mapped to INTISR 7, INTISR 8, and
INTISR 9 in the Cortex-M3 processor NVIC controller. All interrupt enable bits within the NVIC, INTISR 4
through INTISR 9, correspond to bit locations 4 through 9.
Enable SMBus interrupts (I2C_X_SMBALERT and I2C_X_SMBSUS) in the I
2
C peripheral by setting the
appropriate bits in the SMBUS register and clear the appropriate bit in the SMBus register in the interrupt
service routine to prevent a reassertion of the interrupt.
The I2C_X_INT, I2C_X_SMBALERT, and I2C_X_SMBSUS I
2
C interrupt signals can be monitored by the
FPGA logic through the fabric interface interrupt controller (FIIC). Refer to Table 766, page 740 for further
details.
I
2
C
I
2
C Driver Source
Code
APB
Cortex- M3
Processor
SMBus and PMBus Host Controller
( Master /Slave Mode )
SMBus Device
VCC VCC
R
p
R
p
I2C_X_SDAI
I2C_X_SDAO
I2C_X_SCLI
I2C_X_SCLO
I2C_X_SDA
I2C_X_SCL
I2C_X_SMBALERTI
I2C_X_SMBALERTO
VCC
R
p
I2C_X_SMBALERT
MSS GPIO
PMBus Device
I2C_X_PMB_Control
MSS