Fabric Interface Controller
UG0331 User Guide Revision 15.0 760
24.2.2 Master Identity Port to the Fabric
The AHB bus matrix provides a 2-bit side band signal to the FPGA fabric (one 2-bit signal per FIC
instance). The side band signal indicates to the slave, which is implemented in the FPGA fabric, the
identification of the master performing the current transaction. These signals have the same timing as
other AHB Lite master signals such as HTRANS, HMASTLOCK etc. Table 778 on page 760 provides the
decoding of the master accessing the FPGA fabric slave through the MSS AHB bus matrix.
The Libero SoC MSS configurator allows exposure of the master ID port; if the interface is selected to act
as a master of the FPGA fabric.
24.2.3 Configure MSS Master View for the FPGA Fabric Address
There are six 256 MB regions defined as FIC Regions 0 to 5 in the MSS memory map. Each of these
regions can be allocated to the FIC_0 or FIC_1 slave interfaces in a mutually exclusive fashion. Libero
SoC MSS configurator allows you to configure the Memory Regions for the FIC Interfaces. By default,
fabric regions 0, 1, and 2 are accessible through FIC_0 and regions 3, 4, and 5 are accessible through
FIC_1. Table 779, page 760 lists the FIC memory regions.
Table 778 • Master Group Access to Fabric Slaves
FIC_X_MASTER_ID Accessing Master
00 IC-bus, D-bus, and SBus master
01 FIC_0, FIC_1
10 HPDMA, Ethernet MAC, PDMA, USB
11 System controller
Table 779 • FIC Memory Regions
FIC Region Start Address End Address
0 0x30000000 0x3FFFFFFF
1 0x50000000 0x5FFFFFFF
2 0x70000000 0x7FFFFFFF
3 0x80000000 0x8FFFFFFF
4 0x90000000 0x9FFFFFFF
5 0XF0000000 0xFFFFFFFF
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