Microsemi SmartFusion2 - Table 772 INTERRUPT_ENABLE0

Fabric Interface Interrupt Controller
UG0331 User Guide Revision 15.0 750
4 MMUART0_INTR_ENBL 0 MMUART0_INTR interrupt from the MSS MMUART_0
block to fabric.
1: Enable
0: Mask
5 MMUART1_INTR_ENBL 0 MMUART1_INTR interrupt from the MSS MMUART_1
block to fabric.
1: Enable
0: Mask
6 MAC_INT_ENBL 0 MAC_INT interrupt from the MSS Ethernet MAC block to
fabric.
1: Enable
0: Mask
7 USB_MC_INT_ENBL 0 USB_MC_INT interrupt from the MSS USB block to
fabric.
1: Enable
0: Mask
8 PDMAINTERRUPT_ENBL 0 PDMAINTERRUPT interrupt from the MSS peripheral
DMA block to fabric.
1: Enable
0: Mask
9 HPD_XFR_CMP_INT_ENBL 0 HPD_XFR_CMP_INT interrupt from the MSS HPDMA
block to fabric.
1: Enable
0: Mask
10 TIMER1_INTR_ENBL 0 TIMER1_INTR interrupt from the MSS TIMER1 block to
fabric.
1: Enable
0: Mask
11 TIMER2_INTR_ENBL 0 TIMER2_INTR interrupt from the MSS TIMER2 block to
fabric.
1: Enable
0: Mask
12 CAN_INTR_ENBL 0 CAN_INTR interrupt from the MSS CAN controller block
to fabric.
1: Enable
0: Mask
13 RTC_WAKEUP_INTR_ENBL 0 RTC_WAKEUP_INTR interrupt from the MSS RTC block
to fabric.
1: Enable
0: Mask
14 WDOGWAKEUPINT_ENBL 0 WDOGWAKEUPINT interrupt from the MSS Watchdog
block to fabric.
1: Enable
0: MaskThe watchdog is refreshed by writing to the
WDOGREFRESH register. When the counter value is
greater than the value in the WDOGMVRP register and
SLEEPING input to the watchdog is asserted, the
WDOGWAKEUPINT interrupt is generated.
Table 772 • INTERRUPT_ENABLE0 (continued)
Bit
Number
Name
Reset
Value
Description