Microsemi SmartFusion2 - Table 635 Watchdog Timer Register Interface Summary; Wdogload; Wdogmvrp; Wdogrefresh

Watchdog Timer
UG0331 User Guide Revision 15.0 638
20.4 Watchdog Timer Register Map
The following table summarizes the watchdog timer register interface. Detailed description of the
registers is given in Watchdog Timer Configuration Register Bit Definitions, page 638. The base address
for the register details resides at 0x40005000 and extends to the address 0x40005FFF in the Cortex-M3
processor memory map.
20.4.1 Watchdog Timer Configuration Register Bit Definitions
The watchdog timer registers are described in detail in the following tables.
Table 635 • Watchdog Timer Register Interface Summary
Register Name
Address
Offset R/W Reset Source Description
WDOGVALUE 0x00 R WDOGLOAD Current value of the counter
This register is reset with the value in the
WDOGLOAD system register.
WDOGLOAD 0x04 R WDOGLOAD Load value for the counter
This register is reset with the value in the
WDOGLOAD system register.
WDOGMVRP 0x08 R WDOGMVRP Maximum value for which refreshing is permitted.
This register is reset with the value in the
WDOGMVRP system register.
WDOGREFRESH 0x0C W N/A Writing the value 0xAC15DE42 to this register
causes the counter to be updated with the value
in the WDOGLOAD register.
WDOGENABLE 0x10 R WDOGENABLE Watchdog timer enables register
This register is reset with the value in the
WDOGENABLE bit in the WDOG_CR system
register.
WDOGCONTROL 0x14 R/W [31:3] and [1:0]=0X0 Control register
Bit 2 of this register is reset with the value of the
WDOGMODE bit in the WDOG_CR system
register.
Bit 2=WDOGMODE
WDOGSTATUS 0x18 R 0X0 Status register
WDOGRIS 0x1C R/W 0X0 Raw interrupt status
Table 636 • WDOGVALUE
Bit Number Name Reset Value Description
[31:0] WDOGVALUE WDOGLOAD This register contains the current value of the counter in the
watchdog timer. This register is reset with the value in the
WDOGLOAD system register.
Table 637 • WDOGLOAD
Bit Number Name Reset Value Description
[31:0] WDOGLOAD[31:6] WDOGLOAD This register contains the upper 26 bits load value for the counter
in the watchdog timer. This will be updated by the
WDOGLOAD[25:0] bits of the system registers. The least
significant bits of the register always have the value of 0x3F.