Microsemi SmartFusion2 - Table 287 TX_DPKT_BUF_DIS_REG (0 X40043342); Table 288 C_T_UCH_REG (0 X40043344); Table 289 C_T_HHSRTN_REG (0 X40043346); Table 290 C_T_HSBT_REG (0 X40043348)

Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 352
10.3.11.3 TX_DPKT_BUF_DIS_REG Bit Definitions
10.3.11.4 C_T_UCH_REG Bit Definitions
10.3.11.5 C_T_HHRSTN_REG Bit Definitions
10.3.11.6 C_T_HSBT_REG Bit Definitions
Table 287 • TX_DPKT_BUF_DIS_REG (0x40043342)
Bit
Number Name
Reset
Value Function
[15:5] Reserved N/A
4 EP4 TxDPktBufDis 0 Transmit Double Packet Buffer Disable for endpoint 4.
3 EP3 TxDPktBufDis 0 Transmit Double Packet Buffer Disable for endpoint 3.
2 EP2 TxDPktBufDis 0 Transmit Double Packet Buffer Disable for endpoint 2.
1 EP1 TxDPktBufDis 0 Transmit Double Packet Buffer Disable for endpoint 1.
0Reserved N/A
Table 288 • C_T_UCH_REG (0x40043344)
Bit
Number Name
Reset
Value Function
[15:0] C_T_UCH N/A Configurable Chirp Timeout timer. The default value is 203Ah if the host
PHY data width is 16 bits (XCLK is 30 MHz) and 4074h if the PHY data
width is 8 bits (XCLK is 60 MHz), corresponding to a delay of 1.1 ms.
Table 289 • C_T_HHSRTN_REG (0x40043346)
Bit
Number Name
Reset
Value Function
[15:0] C_T_HHRSTN N/A The delay from the end of high speed resumes signaling to enabling
UTM normal operating mode. The default value is 2F3h if the host PHY
data width is 16 bits (XCLK is 30 MHz) and 5E6h if the PHY data width is
8 bits (XCLK is 60 MHz), corresponding to a delay of 100 µs.
Table 290 • C_T_HSBT_REG (0x40043348)
Bit
Number Name
Reset
Value Function
[3:0] HS Timeout Adder 0 The value added to the minimum high speed timeout period (736 bit
times) in increments of 64 high speed bit times. This allows the turn
around timeout period to be set to 16 possible values as given in
Table 291, page 354.