Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 347
10.3.10.6 EPx_TX_MAX_P_REG Bit Definitions
10.3.10.7 EPx_RX_COUNT_REG Bit Definitions
10.3.10.8 EPx_RX_MAX_P_REG Bit Definitions
Table 276 • EPx_TX_MAX_P_REG
Bit
Number Name
Reset
Value Function
[15:11] Reserved N/A
[10:0] EPx_TxMaxP 0 Maximum payload/transaction
Maximum payload in bytes transmitted in a single transaction. The value set can
be up to 1,024 bytes but is subject to the constraints placed by the USB
specification on packet sizes for bulk, interrupt, and ISO transfers in full speed
and high speed operations.
This must be set to an even number of bytes for proper interrupt generation in
DMA mode 1.
Table 277 • EPx_RX_COUNT_REG
Bit
Number Name
Reset
Value Function
[13:0] EPx_Rx Count 0 Holds the number of data bytes in the packet currently in line to be read from the
receive FIFO. If the packet is transmitted as multiple bulk packets, the number
given will be for the combined packet.
The value returned changes as the FIFO is unloaded and is only valid while
RxPktRdy (bit0 in RX_CSRL_REG) is set.
Table 278 • EPx_RX_MAX_P_REG
Bit
Number Name
Reset
Value Function
[15:11] Reserved N/A
[10:0] EPx_RxMaxP 0 Maximum Payload/transaction
Maximum payload in bytes received in a single transaction. The value set can be
up to 1,024 bytes but is subject to the constraints placed by the USB specification
on packet sizes for bulk, interrupt, and ISO transfers in full speed and high speed
operations.
This must be set to an even number of bytes for proper interrupt generation in
DMA Mode 1.
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