Microsemi SmartFusion2 - Figure 35 SCR Bit Assignments; Table 57 SCR Bit Assignments

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 107
Determining preemption of an exception uses only the group priority field, see Interrupt Priority Grouping,
page 41.
3.7.2.6 System Control Register
The SCR controls features of entry to and exit from low power state. See the register summary in
Table 50, page 102 for its attributes. The bit assignments are:
Figure 35 • SCR Bit Assignments
b001 bxxxxxx.yy [7:2] [1:0] 64 4
b010 bxxxxx.yyy [7:3] [2:0] 32 8
b011 bxxxx.yyyy [7:4] [3:0] 16 16
b100 bxxx.yyyyy [7:5] [4:0] 8 32
b101 bxx.yyyyyy [7:6] [5:0] 4 64
b110 bx.yyyyyyy [7] [6:0] 2 128
b111 b.yyyyyyyy None [7:0] 1 256
1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit.
Table 57 • SCR Bit Assignments
Bits Name Function
[31:5] Reserved.
[4] SEVONPEND Send Event on Pending bit:
0: only enabled interrupts or events can wakeup the processor, disabled interrupts are
excluded
1: enabled events and all interrupts, including disabled interrupts, can wakeup the
processor.
When an event or interrupt enters pending state, the event signal wakes up the
processor from WFE. If the processor is not waiting for an event, the event is registered
and affects the next WFE.
The processor also wakes up on execution of an
SEV instruction or an external event.
[3] Reserved.
[2] SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode:
0: sleep
1: deep sleep
Table 56 • Priority Grouping (continued)
PRIGROUP
Interrupt priority level value, PRI_N[7:0] Number of
Binary point
1
Group priority bits Subpriority bits Group priorities Subpriorities
31 4 3 2 1 0
Reserved
Reserved
SLEEPDEEP
SLEEPONEXIT
Reserved
5
SEVONPEND