Microsemi SmartFusion2 - Table 259 ULPI_REG_CTRL (0 X40043076); Table 261 ULPI_RAW_DATA_REG (0 X40043077) (Synchronous)

Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 340
10.3.9.7 ULPI_REG_CTRL Bit Definitions
10.3.9.8 ULPI_RAW_DATA_REG (Asynchronous Mode) Bit Definitions
When one of the PHY’s Asynchronous modes is selected, this register is used to indicate the present
value of the ULPI bus, latched by any transition on int (on data(3)).
10.3.9.9 ULPI_RAW_DATA_REG (Synchronous mode) Bit Definitions
When the PHY’s Synchronous mode is used, this register is used to store the last RxCmd.
Because RxCmds are received in the PHY clock domain and this register is read in the CPU clock domain,
RxCmds may be missed if they are concurrent and the CPU clock is slower than the PHY clock. This should
not be an issue for CarKit negotiation because this process lasts for over 1 ms, but this feature should not
be relied upon to monitor transactions carried out at USB bus speed.
Table 259 • ULPI_REG_CTRL (0x40043076)
Bit
Number Name
Reset
Value Function
[7:3] Reserved N/A
2 ULPIRdnWr 0 Set by software for register read access. Cleared by software for register write
access.
1 ULPIRegCmplt 0 Set by link when register access is complete. This bit must be cleared by
software.
0 ULPIRegReq 0 Set by software to initiate register access. This is cleared when ULPIRegCmplt
(bit 1 of this register) is set.
Table 260 • ULPI_RAW_DATA_REG (0x40043077) (Asynchronous)
Bit
Number Name
Reset
Value Function
[7:4] Reserved N/A
3 data(3) 0 Active high interrupt indication (int)
2 data(2) 0 Single-ended zero (se0)
1 data(1) 0 Differential data (dat)
0 data(0) 0 Active high transmit enable (tx_enable)
Table 261 • ULPI_RAW_DATA_REG (0x40043077) (Synchronous)
Bit
Number Name
Reset
Value Function
7 alt_int 0 Asserted when a non-USB interrupt occurs. In particular, it must be set if an
unmasked event occurs on any bit of the PHY’s CarKit Interrupt Latch register.
6 ID 0 Set to the value of the IDDIG (valid 50 ms after IDPULLUP is asserted).
[5:4] RxEvent[1:0] 0 Encoded UTMI event signals are given in Table 262, page 342.
[3:2] VbusState[1:0] 0 Encoded Vbus voltage state.
00: Vbus < VB_Sess_END
01: VB_Sess_END < = Vbus < VB_Sess_VLD
.
.
10: VB_Sess_VLD < = Vbus < VB_Vbus_VLD
11: VB_Sess_VLD < = Vbus