MMUART Peripherals
UG0331 User Guide Revision 15.0 469
13 MMUART Peripherals
Multi-mode universal asynchronous/synchronous receiver/transmitter (MMUART) performs serial-to-
parallel conversion on data originating from modems or other serial devices, and performs parallel-to-
serial conversion on data from the Cortex-M3 processor or fabric master to these devices. SmartFusion2
SoC FPGAs contain two identical MMUART peripherals in the microcontroller subsystem (MSS
MMUART_0 and MSS MMUART_1), that provide software compatibility with the popular 16550 UART
device.
13.1 Features
SmartFusion2 MMUART peripherals support the following features:
• Asynchronous and synchronous operations
• Full programmable serial interface characteristics
• Data width is programmable to 5, 6, 7, or 8 bits
• Even, odd, or no-parity bit generation/detection
• 1, 1½, and 2 stop bit generation
• 9-bit address flag capability used for multi-drop addressing topologies
• Separate transmit (Tx) and receive (Rx) FIFOs to reduce processor interrupt service loading
• Single-wire half-duplex mode in which Tx pad can be used for bi-directional data transfer
• Local interconnect network (LIN) header detection and auto baud rate calculation
• Communication with ISO 7816 smart cards
• Fractional baud rate capability
• Return to Zero Inverted (RZI) mod/demod blocks that allow infrared data association (IrDA) and
serial infrared (SIR) communications
• The most significant bit (MSB) or the least significant bit (LSB) as the first bit while sending or
receiving data
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