Microsemi SmartFusion2 - Timer X Raw Interrupt Status Register

System Timer
UG0331 User Guide Revision 15.0 624
Timer x Control Register
19.4.4 Timer x Raw Interrupt Status Register
Table 620 • TIMx_CTRL
Bit
Number Name R/W
Reset
Value Description
31:3 Reserved R/W 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 TIMxINTEN R/W 0 Timer x interrupt enable. When the counter reaches zero, an interrupt
is signaled to the Cortex-M3 processor NVIC, IRQ 14 for Timer 1, and
IRQ 15 for Timer 2.
0: Timer x interrupt disabled
1: Timer x interrupt enabled
Writing this register when the Timer is set to 64-bit mode has no effect.
Reading this register when the Timer is set to 64-bit mode returns the
reset value.
1 TIMxMODE R/W 0 Timer x mode.
0: Timer x is in Periodic mode. If TIMxENABLE = 1 when the counter
reaches zero, the counter is reloaded from the value in the
TIMx_LOADVAL register and begins counting down immediately.
1: Timer x is in One-shot mode. If TIMxENABLE = 1, when the counter
reaches zero, the counter stops counting. To start the counter again,
you must load TIMx_LOADVAL with a non-zero value or set the Timer
to Periodic mode by clearing TIMxMODE to 0.
Writing this register when the Timer is set to 64-bit mode has no effect.
Reading this register when the Timer is set to 64-bit mode returns the
reset value.
0 TIMxENABLE R/W 0 Timer x enable.
0: Timer x disabled
1: Timer x enabled
Writing this register when the Timer is set to 64-bit mode has no effect.
Reading this register when the Timer is set to 64-bit mode returns the
reset value.
Table 621 • TIMx_RIS
Bit
Number Name R/W
Reset
Value Description
31:1 Reserved R/W 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 TIMx_RIS R/W 0 Timer x raw interrupt status (RIS)
0: Timer x has not reached zero
1: Timer x has reached zero at least once since this bit was last
cleared (by a reset or by writing 1 to this bit).
Writing a 1 to this bit clears the bit and the interrupt, writing a zero has
no effect.
Writing this register when the Timer is set to 64-bit mode has no effect.
Reading this register when the Timer is set to 64-bit mode returns the
reset value.