Microsemi SmartFusion2 - Table 132 MM4_5_DDR_FIC_SECURITY;MM4_5_FIC64_SECURITY

Embedded SRAM (eSRAM) Controllers
UG0331 User Guide Revision 15.0 203
Note: Refer to Figure 101, page 210 for more information on AHB Bus Matrix masters and slaves.
Table 132 • MM4_5_DDR_FIC_SECURITY/MM4_5_FIC64_SECURITY
Bit
Number Name
Reset
Value Description
[31:10] Reserved 0 Reserved
9 MM4_5_DDR_FIC_MS6_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to
slave 6 (MSS DDR bridge). If not set, masters 4, 5 and
DDR_FIC will not have write access to slave 6.
8 MM4_5_DDR_FIC_MS6_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to
slave 6 (MSS DDR bridge). If not set, masters 4, 5, and
DDR_FIC will not have read access to slave 6.
7 MM4_5_DDR_FIC_MS3_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to
slave 3 (eNVM1). If not set, masters 4, 5, and
DDR_FIC will not have write access to slave 3.
6 MM4_5_DDR_FIC_MS3_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to
slave 3 (eNVM1). If not set, masters 4, 5, and
DDR_FIC will not have read access to slave 3.
5 MM4_5_DDR_FIC_MS2_ALLOWED_W 1 Write Security Bits for masters 4, 5, and DDR_FIC to
slave 2 (eNVM0). If not set, masters 4, 5, and
DDR_FIC will not have write access to slave 2.
4 MM4_5_DDR_FIC_MS2_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to
slave 2 (eNVM0). If not set, masters 4, 5, and
DDR_FIC will not have read access to slave 2.
3 MM4_5_DDR_FIC_MS1_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to
slave 1 (eSRAM1). If not set, masters 4, 5, and
DDR_FIC will not have write access to slave 1.
2 MM4_5_DDR_FIC_MS1_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to
slave 1 (eSRAM1). If not set, masters 4, 5, and
DDR_FIC will not have read access to slave 1.
1 MM4_5_DDR_FIC_MS0_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to
slave 0 (eSRAM0). If not set, masters 4, 5, and
DDR_FIC will not have write access to slave 0.
0 MM4_5_DDR_FIC_MS0_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to
slave 0 (eSRAM0). If not set, masters 4, 5, and
DDR_FIC will not have read access to slave 0.