Cache Controller
UG0331 User Guide Revision 15.0 137
DNC: DCODE Non Cacheable
(W): Write
(R): Read
Table 91 • Data Path for Various Maps
#
Memory Map
Mode Buses
Supported
Trans Region
Destination
Slave Routed Through
1 Default Memory Map - eNVM Remapped
ICODE IC eNVM MS2 AHB Bus Matrix
INC eNVM MS2 AHB Bus Matrix
DCODE DC eNVM MS2 AHB Bus Matrix
DNC eNVM MS0 AHB Bus Matrix
System Bus NC DDR MS5 MSS DDR Bridge
NC NON
DDR
MS1 AHB Bus Matrix
System
Controller Bus
NC DDR MS5 MSS DDR Bridge
NC NON
DDR
MS1 AHB Bus Matrix
2 eSRAM Remapped
ICODE INC eNVM MS2 AHB Bus Matrix
INC DDR MS3 MSS DDR Bridge
INC eSRAM MS2 AHB Bus Matrix
DCODE DNC eNVM MS0 AHB Bus Matrix
DNC (R) DDR MS3 MSS DDR Bridge
DNC (W) DDR MS5 MSS DDR Bridge
DNC eSRAM MS0 AHB Bus Matrix
SBUS NC DDR MS5 MSS DDR Bridge
NC NON
DDR
MS1 AHB Bus Matrix
GBUS NC DDR MS5 MSS DDR Bridge
NC NON
DDR
MS1 AHB Bus Matrix
3 DDR Remapped
ICODE IC DDR MS3 MSS DDR Bridge
INC DDR MS3 MSS DDR Bridge
DCODE DC DDR MS3 MSS DDR Bridge
DNC(R) DDR MS3 MSS DDR Bridge
DNC(W) DDR MS5 MSS DDR Bridge
SBUS NC DDR MS5 MSS DDR Bridge
NC NON
DDR
MS1 AHB Bus Matrix
GBUS NC DDR MS5 MSS DDR Bridge