MMUART Peripherals
UG0331 User Guide Revision 15.0 492
13.4.4 Baud Rate Divisor Registers
Baud rate clock can be generated in three modes: Asynchronous mode, Synchronous Master mode, and
Synchronous Slave mode. Apart from this, MMUART has an option of generating a fractional baud rate
that provides more precision. For more details refer to the Baud Rate Generation, page 474.
13.4.4.1 Asynchronous/Synchronous Mode Context
In Asynchronous mode, the baud rate (BR) clock is generated by dividing the input reference clock's
frequency (APB_0_CLK for MMUART_0 and APB_1_CLK for MMUART_1) by 16 and the integer plus
fractional divisor value, as shown below.
Divisor Value = Integer Value (DMR + DLR registers) plus Fractional Value (DFR/64).
In the Synchronous-Master mode, the baud rate clock is generated by dividing the input reference clock's
frequency (APB_0_CLK for MMUART_0 and APB_1_CLK for MMUART_1) by 2 and the integer divisor
value, as shown below.
DivisorValue = Integer Value (DMR + DLR registers).
In the Synchronous Slave mode, the baud rate clock is generated directly from the input clock, and as
such the divisor registers are not used.
Note: The maximum input clock frequency is 1/2 APB_X_CLK (master clock) frequency, if input filtering is not
used. If input filtering is used, then the maximum input clock frequency is determined by the following
equation:
The glitch filter length (GLR) can be configured by setting the bits in glitch filter register (GFR).
13.4.4.2 Fractional Baud Rate Register
The baud rate divisor value is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
This is used by the baud rate generator to determine the bit period. The fractional baud rate divider
enables the use of any clock with a frequency >3.6864MHz to act as input clock, while it is still possible to
generate all the standard baud rates. The 16-bit integer is written to the integer baud rate register (DLR).
The 6-bit fractional part is written to the fractional baud rate register (DFR). DFRs are accomplished for
divisor values greater than one using time averaging of the two nearest integer value baud rates based
on the fractional value in the DLR:
EQ 1
1 CLEAR_RX_FIFO W 0 Clears all bytes in Rx FIFO and resets counter logic. This
shift register is not cleared.
0: Disabled (default)
1: Enabled
0 ENABLE_TX_RX_FIFO W 1 It enables both the Tx and Rx FIFOs and is hardwired to 1,
which means it is always enabled and cannot be changed.
Table 470 • FCR (continued)
Bit
Number Name R/W
Default
State Description
BaudRate
APB_X_CLK
16DivisorValue
------------------------------------------
=
BaudRate
APB_X_CLK
2DivisorValue
---------------------------------------
=
MaxBaudRate
APB_X_CLK
2 GlitchFilterLength+
------------------------------------------------------------
=
FractionalBaudRate
APB_X_CLK
16 DMR DLR DFR 64++()
------------------------------------------------------------------------------
=
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