Microsemi SmartFusion2 - Figure 289 M3_SYS_RESET_N Generation; Figure 290 MDDR_AXI_RESET_N Generation

Reset Controller
UG0331 User Guide Revision 15.0 657
21.2.6.1.3 T_RESET_N
This is also a reset signal to the Cortex-M3 processor. The T_RESET_N is a synchronized signal of
PO_RESET_N on TRACECLK (Trace clock input from the clock controller). It asserts asynchronously
and negates synchronously to TRACECLK.
21.2.6.1.4 M3_SYS_RESET_N
M3_SYS_RESET_N resets the Cortex-M3 processor core and its components, excluding the debug
logic.
This reset is generated based on M3_RESET_ M3_CLK_N and SYSRESET_N.
M3_RESET_M3_CLK_N is a synchronized signal of M3_RESET_N from the FPGA fabric on M3_CLK.
The generation of M3_SYS_RESET_N is shown in the following figure.
Figure 289 • M3_SYS_RESET_N Generation
In the five Cortex-M3 processor resets, M3_SYS_RESET_N is the only reset signal that can be
controlled.
M3_RESET_N is an active low reset input from the FPGA fabric and resets the Cortex-M3 processors if
set to 0. It is only usable in order to extend the duration of system reset to the Cortex-M3 processor after
the rest of the MSS has been released from reset. This allows to perform a secure hardware based code
shadowing function, thereby minimizing boot time.
21.2.6.1.5 M3_TRST_N
This signal is originates from System Controller and drives the NTRST (debug reset) input of the Cortex-
M3 processor and is used to reset the SWJ-DP sub-block within the Cortex-M3 processor.
21.2.6.2 MDDR Resets
21.2.6.2.1 MDDR_AXI_RESET_N
MDDR_AXI_RESET_N is generated from FPGA fabric reset input (MDDR_DDR_CORE_RESET_N),
SYSRESET_N, and the MDDR soft reset (MDDR_CTLR_SOFTRESET) from SYSREG.
The generation of MDDR_AXI_RESET_N is shown in the following figure.
Figure 290 • MDDR_AXI_RESET_N Generation
The Reset Controller drives a synchronized reset to AXI logic in the MDDR.
21.2.6.2.2 MDDR_APB_RESET_N
MDDR_APB_RESET_N is generated from FPGA fabric PRESET input (MDDR_APB_S_RESET_N) or
SYSRESET_N, based on the selection of MDDR_CONFIG_LOCAL in SYSREG. The
MDDR_CONFIG_LOCAL bit is in the MDDR configuration register (MDDR_CR as defined in Table 648,
page 669) of SYSREG.
M3_SYS_RESET_N
M3_RESET_M3_CLK_N
SYSRESET_N
MDDR_AXI_RESET_N
MDDR_DDR_CORE_RESET_N
SYSRESET_N
MDDR_CTRL_SOFTRESET