Microsemi SmartFusion2 - Figure 54 MPU_RASR Bit Assignments; Table 82 MPU_RASR Bit Assignments

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 126
If the region size is configured to 4GB, in the MPU_RASR, there is no valid ADDR field. In this case, the
region occupies the complete memory map, and the base address is 0x00000000 .
The base address is aligned to the size of the region. For example, a 64KB region must be aligned on a
multiple of 64KB, for example, at
0x00010000 or 0x00020000 .
3.7.4.5 MPU Region Attribute and Size Register
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the
MPU_RNR, and enables that region and any subregions. See the register summary in Table 77,
page 123 for its attributes.
MPU_RASR is accessible using word or halfword accesses:
• the most significant halfword holds the region attributes
• the least significant halfword holds the region size and the region and subregion enable bits.
The bit assignments are:
Figure 54 • MPU_RASR Bit Assignments
For information about access permission, refer to MPU Access Permission Attributes, page 128.
Table 82 • MPU_RASR Bit Assignments
Bits Name Function
[31:29] Reserved.
[28] XN Instruction access disable bit:
0: instruction fetches enabled
1: instruction fetches disabled.
[27] Reserved.
[26:24] AP Access permission field, see Ta ble 8 6, page 129.
[23:22] Reserved.
[21:19, 17, 16] TEX, C, B Memory access attributes, see Table 84, page 128.
[18] S Shareable bit, see Table 84, page 128.
[15:8] SRD Subregion disable bits. For each bit in this field:
0: corresponding sub-region is enabled
1: corresponding sub-region is disabled
See Subregions, page 131 for more information.
Region sizes of 128 bytes and less do not support subregions. When writing the
attributes for such a region, write the SRD field as 0x00.
[7:6] Reserved.
[5:1] SIZE Specifies the size of the MPU protection region. The minimum permitted value is 3
(b00010), see See SIZE Field Values, page 128 for more information.
[0] ENABLE Region enable bit.
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