Microsemi SmartFusion2 - Table 243 MISC_REG (0 X40043061); Table 244 TX_FIFO_SIZE_REG (0 X40043062)

Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 334
10.3.8.3 MISC_REG Bit Definitions
10.3.8.4 TX_FIFO_SIZE_REG Bit Definitions
Table 243 • MISC_REG (0x40043061)
Bit
Number Name
Reset
Value Function
1 TX_EDMA 0 0: DMA_REQ signal for all IN endpoints is deasserted when MAXP
(TX_MAX_P_REG) bytes have been written to an endpoint. This is late mode.
1: DMA_REQ signal for all IN endpoints is deasserted when MAXP-8
(TX_MAX_P_REG-8) bytes have been written to an endpoint. This is early mode.
0 RX_EDMA 0 0: DMA_REQ signal for all OUT endpoints is deasserted when MAXP
(TX_MAX_P_REG) bytes have been read to an endpoint. This is late mode.
1: DMA_REQ signal for all OUT endpoints is deasserted when MAXP-8
(TX_MAX_P_REG-8) bytes have been read to an endpoint. This is early mode.
Table 244 • TX_FIFO_SIZE_REG (0x40043062)
Bit
Number Name
Reset
Value Function
4 DPB 0 Defines whether double-packet buffering is supported. When ‘1’, double-
packet buffering is supported. When ‘0’, only single-packet buffering is
supported.
[3:0] SZ[3:0] 0 Maximum packet size to be allowed for (before any splitting within the FIFO of
bulk/high-bandwidth packets prior to transmission).
00
00: 8 Bytes
0
001: 16 Bytes
0010: 32 Bytes
0011: 64 Bytes
0100: 128 Bytes
0101: 256 Bytes
0110: 512 Bytes
0111: 1,024 Bytes
1000: 2,048 Bytes
1001: 4,096 Bytes
If DPB = 0, the FIFO will also be this size; if DPB = 1, the FIFO will be twice
this size.