Microsemi SmartFusion2 - Mac_Stat_Clronrd_Cr; Reset_Source_Cr; Cc_Dc_Err_Addr_Sr; Cc_Ic_Err_Addr_Sr

System Register Block
UG0331 User Guide Revision 15.0 678
MAC_CR 0x8C RW-P Register SYSRESET_
N
MAC Configuration Register
MSSDDR_PLL_STATUS_LOW
_CR
0x90 RW-P Register CC_RESET_
N
Controls the configuration input
of MPLL register
MSSDDR_PLL_STATUS_HIG
H_CR
0x94 RW-P Register CC_RESET_
N
Controls the configuration input
of MPLL register
MSSDDR_FACC1_CR 0x98 RW-P Field CC_RESET_
N
MSS DDR bridge FACC1
Configuration Register
MSSDDR_FACC2_CR 0x9C RW-P Field CC_RESET_
N
MSS DDR bridge FACC2
Configuration Register
PLL_LOCK_EN_CR 0xA0 RW-P Register CC_RESET_
N
PPL Lock Enable Control
Register
MSSDDR_CLK_CALIB_CR 0xA4 RW-P Register SYSRESET_
N
Starts FPGA fabric calibration
test circuit
PLL_DELAY_LINE_SEL_CR 0xA8 RW-P Register SYSRESET_
N
PLL Delay Line Select Control
Register
MAC_STAT_CLRONRD_CR 0xAC RW-P Register SYSRESET_
N
MAC status clear on read
RESET_SOURCE_CR 0xB0 RW Reset Source Control Register
CC_DC_ERR_ADDR_SR 0xB4 RO SYSRESET_
N
Dcode Bus Error Address Status
Register
CC_IC_ERR_ADDR_SR 0xB8 RO SYSRESET_
N
Icode Bus Error Address Status
Register
CC_SB_ERR_ADDR_SR 0xBC RO SYSRESET_
N
System Bus Error Address
Status Register
Reserved 0xC0 SYSRESET_
N
CC_IC_MISS_CNTR_SR 0xC4 RO SYSRESET_
N
ICode Miss Control Status
Register
CC_IC_HIT_CNTR_SR 0xC8 RO SYSRESET_
N
ICode Hit Control Status
Register
CC_DC_MISS_CNTR_SR 0xCC RO SYSRESET_
N
DCode Miss Control Status
Register
CC_DC_HIT_CNTR_CR 0xD0 RO SYSRESET_
N
DCode Hit Control Status
Register
CC_IC_TRANS_CNTR_SR 0xD4 RO SYSRESET_
N
ICode Transaction Count
Control Status Register
CC_DC_TRANS_CNTR_SR 0xD8 RO SYSRESET_
N
DCode Transaction count
Control Status Register
DDRB_DS_ERR_ADR_SR 0xDC RO SYSRESET_
N
MSS DDR Bridge DS Master
Error Address Status Register
Table 650 • SYSREG (continued)
Register Name
Addr.
Offset
Register
Type
Flash
Write
Protect Reset Source Description