APB Configuration Interface
UG0331 User Guide Revision 15.0 785
The APB configuration space is divided into multiple partitions; each partition is reserved to one specific
module or type of functionality. The APB addresses are word aligned.
The base address of FDDR, SERDESIF0, and SERDESIF1 configuration address space resides at
0x40020400 and extends to address 0x4002FFFF in the memory map of the Cortex-M3 processor on the
AHB bus matrix.
• Refer to the "Fabric Double Data Rate Subsystem" chapter in the UG0446: SmartFusion2 and
IGLOO2 FPGA High Speed DDR Interfaces User Guide for FDDR register map details and address
space partition.
• Refer to the "Serializer/Deserializer" chapter of the UG0447: SmartFusion2 and IGLOO2 FPGA High
Speed Serial Interfaces User Guide for SERDES register map details and address space partition.
The base address of the MDDR configuration address space resides at 0x40020000 and extends to
address 0x400203FF in the memory map of the Cortex-M3 processor on the AHB bus matrix.
• Refer to the "MSS DDR Subsystem" chapter of the UG0446: SmartFusion2 and IGLOO2 FPGA
High Speed DDR Interfaces User Guide for MDDR register map details and address space partition.
25.1.2 Port List
Table 783 • FDDR APB Slave Configuration Interface Port List
Port Name Direction Polarity Description
APB_S_PSEL In High Indicates APB slave select
APB_S_PENABLE In High Indicates APB enable
APB_S_PWRITE In High APB write control signal. Indicates read when Low
and write when High.
APB_S_PADDR [10:2] In Indicates APB address. Addresses are word aligned.
APB_S_PWDATA [15:0] In Indicates APB write data
APB_S_PRDATA [15:0] Out Indicates APB read data
APB_S_PREADY Out Indicates APB PREADY signal and is used to extend
an APB transfer.
APB_S_PSLVERR Out High Indicates a transfer failure
APB_S_PCLK In Indicates APB clock
APB_S_PRESET_N In Low Indicates APB active low reset
Table 784 • MDDR APB Slave Configuration Interface Port List
Port Name Direction Polarity Description
MDDR_APB_S_PSEL In High Indicates APB slave select
MDDR_APB_S_PENABLE In High Indicates APB enable
MDDR_APB_S_PWRITE In High APB write control signal. Indicates read when Low and
write when High.
MDDR_APB_S_PADDR [10:2] In Indicates APB address. Addresses are word aligned.
MDDR_APB_S_PWDATA [15:0] In Indicates APB write data
MDDR_APB_S_PRDATA [15:0] Out Indicates APB read data
MDDR_APB_S_PREADY Out Indicates APB PREADY signal and used to extend an
APB transfer.
MDDR_APB_S_PSLVERR Out High Indicates a transfer failure
MDDR_APB_S_PCLK In Indicates APB clock
MDDR_APB_S_PRESET_N In Low Indicates APB active low reset
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