Microsemi SmartFusion2 - Table 168 HPDMAD1 PTR_REG

High Performance DMA Controller
UG0331 User Guide Revision 15.0 260
8.4.1.19 Descriptor 1 Pending Transfers Register
8.4.1.20 Descriptor 2 Pending Transfers Register
Table 168 • HPDMAD1PTR_REG
Bit
Number Name
Reset
Value Description
15:0 HPDMAPTR_D1_SRC_PNDNG 0 Descriptor 1 source pending transfers in words.
This register indicates the internal transfer size counter
corresponding to the source end of descriptor 1.
At the end of the transfer, zero in this register indicates the
successful transfer, and a non-zero value indicates error
occurrence at the source during descriptor 1 transfer.
31:16 HPDMAPTR_D1_DST_PNDNG 0 Descriptor 1 destination pending transfers in words.
This register indicates the internal transfer size counter
corresponding to the destination end of descriptor 1.
At the end of the transfer, zero in this register indicates the
successful transfer, and a non-zero value indicates error
occurrence at the destination during descriptor 1 transfer.
Table 169 • HPDMAD2PTR_REG
Bit
Number Name
Reset
Value Description
15:0 HPDMAPTR_D2_SRC_PNDNG 0 Descriptor 2 source pending transfers in words.
This register indicates the internal transfer size counter
corresponding to the source end of descriptor 2.
At the end of the transfer, zero in this register indicates the
successful transfer, and a non-zero value indicates error
occurrence at the source during descriptor 2 transfer.
31:16 HPDMAPTR_D2_DST_PNDNG 0 Descriptor 2 destination pending transfers in words.
This register indicates the internal transfer size counter
corresponding to the destination end of descriptor 2.
At the end of the transfer, zero in this register indicates the
successful transfer, and a non-zero value indicates error
occurrence at the destination during descriptor 2 transfer.