MMUART Peripherals
UG0331 User Guide Revision 15.0 501
13.4.15 Multi-Mode Control Register 1 (MM1)
13.4.16 Multi-Mode Control Register 2 (MM2)
Table 486 • MM1
Bit
Number Name R/W
Default
State Description
[7:6] Reserved R/W 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read- modify-write operation.
5 EITP R/W 0 Output pulse width for RZI mod can be modified using this bit.
0: 3/16
th
Tbit pulse width (default).
1: 1/4
th
Tbit pulse width.
4 EITX R/W 0 You can configure output polarity for RZI modulation.
0: RZI output pulses are active Low and signify a low NRZ value (default).
1: RZI output pulses are active High and signify a high NRZ value.
3 EIRX R/W 0 You can configure input polarity for RZI demodulation.
0: RZI input pulses are active Low, signifying a low NRZ value (default).
1: RZI input pulses are active High, signifying a high NRZ value.
2 EIRD R/W 0 Enables RZI modulation/demodulation.
0: Disabled (default)
1: Enabled
1 E_MSB_TX R/W 0 LSB or MSB can be sent first by configuring this bit. By default, the "THR"
bit 0 is the LSB, and is the first transmitted bit. Bit 0 of the THR may be
configured as the last transmitted bit, MSB.
0: THR's bit 0 is the first transmitted bit, LSB (default).
1: THR's bit 0 is the last transmitted bit, MSB.
0 E_MSB_RX R/W 0 LSB or MSB can be received first by configuring this bit. By default, the
receiver buffer register's (RBR) bit 0 is the LSB, and is the first received
bit. Bit 0 of the RBR may be configured as the last received bit, MSB.
0: RBR's bit 0 is the first received bit, LSB (default).
1: RBR's bit 0 is the last received bit, MSB.
Table 487 • MM2
Bit
Number Name R/W
Reset
Value Description
[7:4] Reserved R/W 0 The software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read- modify-write operation.
3 ESWM R/W 0 Enable single-wire, half-duplex mode.
0: Disabled (default)
1: Enabled
2 EAFC R/W 0 Enable a flag clear (EAFC). When EAFM is enabled the Rx FIFO is
disabled until another address flag with matching address is received. The
bit gets cleared on write in multi-mode control registers 2.
0: Disabled (default)
1: Enabled
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