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Microsemi SmartFusion2 - Instruction Set Summary; Table 26 Cortex-M3 Processor Instructions; Table 491 ADR

Microsemi SmartFusion2
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Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 46
3.5.5.4 External Event Input
The processor provides an external event input signal. Peripherals can drive this signal, either to wake
the processor from WFE, or to set the internal WFE event register to one to indicate that the processor
must not enter Sleep mode on a later WFE instruction. See Wait for Event, page 46 for more information.
3.5.5.5 Power Management Programming Hints
ISO/IEC C cannot directly generate the
WFI
and
WFE
instructions. The CMSIS provides the following
functions for these instructions:
void __WFE(void) // Wait for Event
void __WFI(void) // Wait for Interrupt
3.6 Cortex-M3 Processor Instruction Set
This section is the reference material for the Cortex-M3 processor instruction set description in this user
guide.
3.6.1 Instruction Set Summary
The processor implements a version of the Thumb instruction set. The following table lists the supported
instructions.
In the following table:
angle brackets, <>, enclose alternative forms of the operand
braces, {}, enclose optional operands
the Operands column is not exhaustive
Op2
is a flexible second operand that can be either a register or a constant
most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Table 26 • Cortex-M3 Processor Instructions
Mnemonic Operands Brief description Flags
ADC, ADCS
{Rd,}
Rn,
Op2
Add with Carry N, Z, C, V
ADD, ADDS
{Rd,}
Rn, Op2
Add N, Z, C, V
ADD, ADDW
{Rd,}
Rn, #imm12
Add N, Z, C, V
ADR Rd, label Load PC-relative Address
AND, ANDS {Rd,} Rn, Op2 Logical AND N, Z, C
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N, Z, C
B label Branch
BFC Rd, #lsb, #width Bit Field Clear
BFI Rd, Rn, #lsb, #width Bit Field Insert
BIC, BICS
{Rd,}
Rn, Op2
Bit Clear N, Z, C
BKPT #imm Breakpoint
BL label Branch with Link
BLX Rm Branch indirect with Link
BX Rm Branch indirect
CBNZ Rn, label Compare and Branch if Non Zero
CBZ Rn, label Compare and Branch if Zero
CLREX Clear Exclusive

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