Microsemi SmartFusion2 - RTC Wake up Configuration Register

System Register Block
UG0331 User Guide Revision 15.0 702
MSS Interrupt Enable Control Register
Note: Do not change these register fields dynamically for 005 and 010 devices, see System Registers Behavior
for M2S005/010 Devices, page 682.
22.3.34 RTC Wake Up Configuration Register
Note: Do not change these register fields dynamically for 005 and 010 devices, see System Registers Behavior
for M2S005/010 Devices, page 682.
22.3.35 MAC Configuration Register
Table 688 • MSS_IRQ_ENABLE_CR
Bit
Number Name
Reset
Value Description
[31:20] Reserved 0
[19:10] DDRB_INTERRUPT_EN 0x3FF Used to mask the MSS DDR bridge interrupt to the Cortex-M3
processor
[9:7] CC_INTERRUPT_EN 0x7 Used to mask the cache interrupt to the Cortex-M3 processor
[6:0] SW_INTERRUPT_EN 0x7F Used to mask the AHB bus interrupt to the Cortex-M3
processor
Table 689 • RTC_WAKEUP_CR
Bit
Number Name
Reset
Value Description
[31:3] Reserved 0
2 RTC_WAKEUP_C_EN 0 Enables RTC_WAKEUP interrupt to the system controller
1 RTC_WAKEUP_FAB_EN 0 Enables the RTC_WAKEUP interrupt to the fabric
0 RTC_WAKEUP_M3_EN 0 Enables the RTC_WAKEUP interrupt to the Cortex-M3
processor
Table 690 • MAC_CR
Bit
Number Name
Reset
Value Description
[31:9] Reserved 0
[8:5] RGMII_TXC_DELAY_SEL 0 Specifies how many delay taps the RGMII transmit clock
passes through 0 to 15
[3:2] ETH_PHY_MODE 0 Indicates the Ethernet PHY mode. Allowed values:
000: RMII
001: Reserved
010: TBI
011: MII
100: GMII
Other values: Reserved
[1:0] ETH_LINE_SPEED 0 Indicates the Ethernet line speed. Allowed values:
00: 10 Mbps
01: 100 Mbps
10: 1,000 Mbps
11: Reserved